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SN74F323 Datasheet

8-Bit Universal Shift-Storage Register

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SN74F323
8ĆBIT UNIVERSAL SHIFTĆSTORAGE REGISTER
WITH SYNCHRONOUS CLEAR AND 3ĆSTATE OUTPUTS
SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993
Four Modes of Operation:
Hold (Store)
Shift Right
Shift Left
Load Data
Operates With Outputs Enabled or at High
Impedance
3-State Outputs Drive Bus Lines Directly
Can Be Cascaded for N-Bit Word Lengths
Synchronous Clear
Applications:
Stacked or Push-Down Registers
Buffer Storage
Accumulator Registers
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
DW OR N PACKAGE
(TOP VIEW)
S0
OE1
OE2
G/QG
E/QE
C/QC
A /QA
QA
CLR
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 S1
18 SL
17 QH
16 H/QH
15 F/QF
14 D/QD
13 B/QB
12 CLK
11 SR
description
This 8-bit universal register features multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin
package. Two function-select (S0, S1) and two output-enable (OE1, OE2) inputs can be used to choose the
modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs
in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register.
Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs
synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but this
has no effect on clearing, shifting, or storage of data.
The SN74F323 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
MODE CLR S1 S0 OE1† OE2† CLK SL SR A /QA B/QB
L XL L
L XX L
L
C/QC
L
I/O PORTS
D/QD E/QE
LL
F/QF
L
G/QG H/QH
LL
OUTPUTS
QAQH
LL
Clear L L X L L X X L L L L L L L L L L
L HH X X X X X X X X X X X X L L
H LL
Hold
H XX
Shift H L H
Right H L H
Shift H H L
Left H H L
Load H H H
L
L
L
L
L
L
X
L X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0
L L X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0
L X H H QAn QBn QCn QDn QEn QFn QGn H QGn
L X L L QAn QBn QCn QDn QEn QFn QGn L QGn
L H X QBn QCn QDn QEn QFn QGn QHn H QBn H
L L X QBn QCn QDn QEn QFn QGn QHn L QBn L
X XX a
b
c
d
e
f
g
h ah
NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. These data inputs are loaded into the flip-flops while the
flip-flop outputs are isolated from the I/O terminals.
When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
2−1


Texas Instruments (TI) Electronic Components Datasheet

SN74F323 Datasheet

8-Bit Universal Shift-Storage Register

No Preview Available !

SN74F323
8ĆBIT UNIVERSAL SHIFTĆSTORAGE REGISTER
WITH SYNCHRONOUS CLEAR AND 3ĆSTATE OUTPUTS
SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993
logic symbol
CLR
OE1
OE2
S0
S1
CLK
SR
A /QA
9
2
3
1
19
12
11
7
13
B /QB
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH
6
14
5
15
4
16
18
SL
SRG8
4R
&
3EN5
00
1 M3
C4/1/2
1, 4D
3, 4D
5
3, 4D
5
3, 4D
5
2, 4D
8
QA
17
QH
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2−2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443


Part Number SN74F323
Description 8-Bit Universal Shift-Storage Register
Maker Texas
Total Page 8 Pages
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