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Texas Instruments (TI) Electronic Components Datasheet

SN74BCT979 Datasheet

9-Bit Registered BTL Transceiver

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BiCMOS Design Significantly Reduces ICCZ
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Support IEEE BTL Standard 1194.1-1991
Open-Collector B Port Drives Load
Impedances as Low as 10
BTL Logic Level 1-V Bus Swing Reduces
Power Consumption
Latchable Transceiver With Output Sink
of 24 mA at the A Bus and 100 mA at the
B Bus
Option to Generate and Check Parity or
Feed-Through Data/Parity in Directions
A to B or B to A
Independent Latch Enables for A-to-B
and B-to-A Directions
Select Pin for ODD/EVEN Parity
ERRA and ERRB Output Pins for Parity
Checking
Ability to Simultaneously Generate and
Check Parity
Packaged in 300-mil Plastic Shrink
Small-Outline (DL) Package
SN74BCT979
9ĆBIT REGISTERED BTL TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
DL PACKAGE
(TOP VIEW)
VCC
AI1
AO1
AI2
AO2
GND
AI3
AO3
AI4
AO4
AI5
GND
AO5
AI6
AO6
AI7
AO7
GND
AI8
AO8
APARI
APARO
VCC
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 OEBA
47 LEAB
46 B1
45 GND
44 GND
43 B2
42 ERRA
41 B3
40 GND
39 GND
38 B4
37 ODD/EVEN
36 B5
35 SEL
34 B6
33 GND
32 GND
31 B7
30 ERRB
29 B8
28 GND
27 GND
26 BPAR
25 OEAB
description
The SN74BCT979 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a
feed-through transceiver, or it can generate/check parity from the 8-bit data bus in either direction. It has a
guaranteed current-sinking capability of 24 mA at the A bus and 100 mA at the open-collector B bus.
The SN74BCT979 features independent latch-enable (LEAB, LEBA) inputs for the A-to-B direction and the
B-to-A direction, an ODD/EVEN input to select odd or even parity, and separate error-signal (ERRA, ERRB)
outputs for checking parity.
When communication between buses occurs, parity is generated and passed on to either bus as APARO or
BPAR. Error detection of the parity generated from AI1−AI8 and B1−B8 can be checked by ERRA and ERRB,
providing LEAB and LEBA are high and the mode select (SEL) is low. If SEL is high, the communication between
buses is in a feed-through mode where parity is still generated and checked as ERRA and ERRB.
The SN74BCT979 features open-collector driver outputs (B port) with a series Schottky diode to reduce
capacitive loading to the bus. By using a 2-V pullup on the bus, the output signal swing will be approximately
1 V, which reduces the power necessary to drive the bus load capacitance. The driver outputs are capable of
driving an equivalent dc load of as low as 10 .
The transceiver has a precision threshold set by an internal bandgap reference to give accurate input thresholds
over VCC and temperature variations.
This transceiver is compatible with backplane transceiver logic (BTL) technology at significantly reduced power
dissipation per channel.
The SN74BCT979 is characterized for operation from 0°C to 70°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1


Texas Instruments (TI) Electronic Components Datasheet

SN74BCT979 Datasheet

9-Bit Registered BTL Transceiver

No Preview Available !

SN74BCT979
9ĆBIT REGISTERED BTL TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS115A − OCTOBER 1990 − REVISED NOVEMBER 1993
FUNCTION TABLE
INPUTS
OEAB OEBA SEL LEAB LEBA
OPERATION OR FUNCTION†
H H X X X Isolation. AO1 −AO8 /APARO are in the high-impedance state and B1 −B8 /APAR are high.
H
L
L
X
H
Parity is generated from B1 −B8 data and output on APARO and is checked against BPAR and
output on ERRB.
Parity is generated from latched B1 −B8 data and output on APARO and is checked against BPAR
H L L X L and output on ERRB.
H
L
H
X
H
BPAR is output on APARO. Parity is generated from B1 −B8 data, checked against BPAR, and
output on ERRB.
H
L
HX
L
BPAR is output on APARO. Parity is generated from latched B1 −B8 data, checked against BPAR,
and output on ERRB.
Parity is generated from AI1 −AI8 data and output on BPAR and is checked against APARI and
L H L H X output on ERRA.
L
H
L
L
X
Parity is generated from latched AI1 −AI8 data and output on BPAR and is checked against APARI
and output on ERRA.
L
H
H
H
X
APARI is output on BPAR. Parity is generated from AI1 −AI8 data, checked against APARI, and
output on ERRA.
L
H
H
L
X
APARI is output on BPAR. Parity is generated from latched AI1 −AI8 data, checked against APARI,
and output on ERRA.
L L X X X AO1 −AO8 /APARO and B1 −B8 /BPAR are active (high or low logic levels).
Parity is generated from AI1 −AI8 and from B1 − B8 based on the level present at ODD/EVEN. Parity is checked (AI1 − AI8 against APARI and
B1 −B8 against BPAR) based on the level present at ODD/EVEN (see parity function table).
PARITY FUNCTION TABLE‡
INPUTS
OUTPUTS
OEAB
SEL
ODD/EVEN
Σ OF INPUTS
AI1 −AI8 = H
APARI
BPAR ERRA
LL
L
0, 2, 4, 6, 8
L
LH
LL
L
1, 3, 5, 7 L H L
LL
L
0, 2, 4, 6, 8
H
L
L
LL
L
1, 3, 5, 7 H H H
LL
H
0, 2, 4, 6, 8
L
H
L
LL
H
1, 3, 5, 7 L L H
LL
H
0, 2, 4, 6, 8
H
HH
LL
H
1, 3, 5, 7 H L L
LH
L
0, 2, 4, 6, 8
L
LH
LH
L
1, 3, 5, 7 L L L
LH
L
0, 2, 4, 6, 8
H
H
L
LH
L
1, 3, 5, 7 H H H
LH
H
0, 2, 4, 6, 8
L
LL
LH
H
1, 3, 5, 7 L L H
LH
H
0, 2, 4, 6, 8
H
HH
LH
H
1, 3, 5, 7 H H L
HX
X
X X HX
Parity functions for the A bus are shown. Parity functions for the B bus are
similar, but use B1 −B8 and BPAR as inputs and APARO and ERRB as outputs.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443


Part Number SN74BCT979
Description 9-Bit Registered BTL Transceiver
Maker Texas
Total Page 10 Pages
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