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Texas Instruments (TI) Electronic Components Datasheet

SN74BCT899 Datasheet

9-Bit Latchable Transceiver

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State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
Simultaneously Generates and Checks
Parity
Packaged in Plastic Small-Outline Package
description
The SN74BCT899 is a 9-bit to 9-bit parity
transceiver with transparent latches. The device
can operate as a feed-through transceiver or it can
generate/check parity from the 8-bit data buses in
either direction. It has a current-sinking capability
of 24 mA at the A bus and 64 mA at the B bus.
The SN74BCT899 features independent latch-
enable (LEAB or LEBA) inputs, a select (SEL)
input for ODD/EVEN parity, and separate
error-signal (ERRA or ERRB) outputs for checking
parity.
The SN74BCT899 is characterized for operation
from 0°C to 70°C.
SN74BCT899
9ĆBIT LATCHABLE TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993
DW PACKAGE
(TOP VIEW)
ODD/EVEN
ERRA
LEAB
A1
A2
A3
A4
A5
A6
A7
A8
APAR
OEBA
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 OEAB
26 B1
25 B2
24 B3
23 B4
22 B5
21 B6
20 B7
19 B8
18 BPAR
17 LEBA
16 SEL
15 ERRB
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1993, Texas Instruments Incorporated
2−1


Texas Instruments (TI) Electronic Components Datasheet

SN74BCT899 Datasheet

9-Bit Latchable Transceiver

No Preview Available !

SN74BCT899
9ĆBIT LATCHABLE TRANSCEIVER
WITH PARITY GENERATOR/CHECKER
SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993
OEAB
H
H
H
H
H
H
L
L
L
L
L
L
FUNCTION TABLE
INPUTS
OEBA SEL LEAB LEBA
OPERATION OR FUNCTION
H X X X Buses A and B are in the high-impedance state.
L
L
X
H
Generates parity from B1 −B8 based on ODD/EVEN. Generated parity APAR. Generated parity
checked against BPAR and output as ERRB.
Generates parity from B1 −B8 based on ODD/EVEN. Generated parity APAR. Generated parity
L L H H checked against BPAR and output as ERRB. Generated parity also fed back through the A latch
for generate/check as ERRA.
L
L
X
L
Generates parity from B-latch data based on ODD/EVEN. Generated parity APAR. Generated
parity checked against latched BPAR and output as ERRB.
L
H
X
H
BPAR /B1 −B8 APAR/A1 −A8 feed-through mode. Generated parity checked against BPAR and
output as ERRB.
L
H
H
H
BPAR /B1 −B8 APAR/A1 −A8 feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA.
H
L
H
X
Generates parity from A1 −A8 based on ODD/EVEN. Generated parity BPAR. Generated parity
checked against APAR and output as ERRA.
Generates parity from A1 −A8 based on ODD/EVEN. Generated parity BPAR. Generated parity
H L H H checked against APAR and output as ERRA. Generated parity also fed back through the B latch
for generate/check as ERRB.
H
L
L
X
Generates parity from A-latch data based on ODD/EVEN. Generated parity BPAR. Generated
parity checked against latched APAR and output as ERRA.
H
H
H
X
APAR /A1 −A8 BPAR/B1−B8 feed-through mode. Generated parity checked against APAR and
output as ERRA.
H
H
H
X
APAR /A1 −A8 BPAR/B1−B8 feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB.
L X X X Output to A bus and B bus
PARITY FUNCTION TABLE
INPUTS†
OUTPUTS
ODD/EVEN
Σ OF INPUTS
A1 −A8 = H
APAR
BPAR‡
ERRA
L
0, 2, 4, 6, 8
L
L
H
L 1, 3, 5, 7 L H L
L
0, 2, 4, 6, 8
H
L
L
L 1, 3, 5, 7 H H H
H
0, 2, 4, 6, 8
L
H
L
H 1, 3, 5, 7 L L H
H
0, 2, 4, 6, 8
H
H
H
H
1, 3, 5, 7
H
L
L
If LE = H, current A1 −A8 and APAR data is used. If LE = L,
latched A1−A8 and APAR data is used.
This is the value of BPAR if SEL = L. If SEL = H, BPAR = APAR.
2−2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74BCT899
Description 9-Bit Latchable Transceiver
Maker Texas
Total Page 8 Pages
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