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Texas Instruments (TI) Electronic Components Datasheet

SN74BCT29853 Datasheet

8-Bit To 9-Bit Parity Bus Transceiver

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BiCMOS Process With TTL Inputs and
Outputs
State-of-the-Art BiCMOS Design
Significantly Reduces Standby Current
Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
Functionally Equivalent to AMD Am29853
High-Speed Bus Transceiver With Parity
Generator/ Checker
Parity-Error Flag With Open-Collector
Output
Latch for Storage of the Parity-Error Flag
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
SN74BCT29853
8ĆBIT TO 9ĆBIT PARITY BUS TRANSCEIVER
ą
SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994
DW OR NT PACKAGE
(TOP VIEW)
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 B1
22 B2
21 B3
20 B4
19 B5
18 B6
17 B7
16 B8
15 PARITY
14 OEB
13 LE
description
The SN74BCT29853 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator/ checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-erro (ERR)r flag. ERR can be either passed, sampled, stored, or cleared from the
latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is
transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition
which gives the designer more system diagnostic capability. The SN74BCT29853 provides true logic.
The SN74BCT29853 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
OEB
OEA
INPUTS
CLR
LE
Ai
of H’s
Bi†
of H’s
OUTPUT AND I/O
A B PARITY ERR‡
L
H
X
X
Odd
Even
NA NA A
L
H
NA
HLXL
NA
Odd
Even
B NA
NA
H
L
H L HH
NA
X X NA NA N−1
XXLH
X
X
X NA
NA
H
HH
X
H
H
L
X
H
L
X
L Odd
X L H Even
X
NC
ZZ
Z
H
H
L
L
L
X
X
Odd
Even
NA NA A
H
L
NA
NA = not applicable, NC = no change, X = don’t care
Summation of high-level inputs includes PARITY along with Bi inputs.
Output states shown assume the ERR output was previously high.
§ In this mode, the ERR output, when enabled, shows inverted parity of the A bus.
FUNCTION
A data to B bus and generate parity
B data to A bus and check parity
Store error flag
Clear error-flag register
Isolation§ (parity check)
A data to B bus and generate inverted
parity
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1994, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
2−1


Texas Instruments (TI) Electronic Components Datasheet

SN74BCT29853 Datasheet

8-Bit To 9-Bit Parity Bus Transceiver

No Preview Available !

SN74BCT29853
8ĆBIT TO 9ĆBIT PARITY BUS TRANSCEIVER
ą
SCBS002D − SEPTEMBER 1987 − REVISED APRIL 1994
logic diagram (positive logic)
A1 −A8
8
8x
EN
8x
EN
8
OEB
OEA
LE
CLR
8
8
MUX
1
1
9 2k
1
1
G1
P
8
B1 −B8
PARITY
ERR
2−2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443


Part Number SN74BCT29853
Description 8-Bit To 9-Bit Parity Bus Transceiver
Maker Texas
Total Page 9 Pages
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