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Texas Instruments (TI) Electronic Components Datasheet

SN74BCT29846 Datasheet

8-Bit Bus-Interface D-Type Latch

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BiCMOS Process With CMOS Inputs and
TTL Outputs Substantially Reduces
Standby Current
Input Has 50-Pullup Resister
Bus-Structured Pinout
Functionally Equivalent to SN74ALS29846
and AMD Am29846
Provides Extra Data Width Necessary For
Wider Address / Data Paths or Buses With
Parity
Power-Up High-Impedance State
Buffered Control Inputs to Reduce
DC Loading Effects
Packaged in Standard Plastic 300-mil
DIP (NT)
SN74BCT29846
8ĆBIT BUSĆINTERFACE DĆTYPE LATCH
WITH 3ĆSTATE OUTPUTS
SCBS023C − MARCH 1989 − REVISED APRIL 1994
NT PACKAGE
(TOP VIEW)
OE1
OE2
1D
2D
3D
4D
5D
6D
7D
8D
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 OE3
22 1Q
21 2Q
20 3Q
19 4Q
18 5Q
17 6Q
16 7Q
15 8Q
14 PRE
13 LE
description
The SN74BCT29846 features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight latches of the SN74BCT29846 are transparent D-type latches. The SN74BCT29846 has inverting
data (D) inputs. Since clear (CLR) and preset (PRE) are independent of the clock, taking the CLR input low will
cause the eight Q outputs to go low. Taking the PRE input low will cause the eight Q outputs to go high. When
both PRE and CLR are taken low, the outputs will follow the preset condition.
The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a
normal logic state (high or low levels) or a high-impedance state. The outputs are also in the high-impedance
state during power-up and power-down conditions. The outputs remain in the high-impedance state while the
device is powered-down. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a
bus-organized system without need for interface or pull-up components. The output enables do not affect the
internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in
the high-impedance state.
The SN74BCT29846 is characterized for operation from 0°C to 70°C.
PRE
L
H
H
H
H
X
X
X
CLR
X
L
H
H
H
X
X
X
FUNCTION TABLE
INPUTS
OE1 OE2 OE3 LE
LLLX
LLLX
L L LH
L L LH
LLLL
XXHX
XHXX
HXXX
OUTPUT
DQ
XH
XL
LH
HL
X Q0
XZ
XZ
XZ
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1994, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1


Texas Instruments (TI) Electronic Components Datasheet

SN74BCT29846 Datasheet

8-Bit Bus-Interface D-Type Latch

No Preview Available !

SN74BCT29846
8ĆBIT BUSĆINTERFACE DĆTYPE LATCH
WITH 3ĆSTATE OUTPUTS
SCBS023C − MARCH 1989 − REVISED APRIL 1994
logic symbol
OE1
OE2
OE3
PRE
CLR
LE
1D
2D
3D
4D
5D
6D
7D
8D
1
2
23
14
11
13
3
4
5
6
7
8
9
10
&
S2
R
C1
1D
EN
2
22
1Q
21
2Q
20
3Q
19
4Q
18
5Q
17
6Q
16
7Q
15
8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
OE1
OE2
OE3
PRE
1
2
23
14
LE 13
3
1D
S2
C1
1D 2
R
4
2D
S2
C1
1D 2
R
5
3D
S2
C1
1D 2
R
6
4D
S2
C1
1D 2
R
7
5D
S2
C1
1D 2
R
8
6D
S2
C1
1D 2
R
9
7D
S2
C1
1D 2
R
10
8D
11
CLR
S2
C1
1D 2
R
22
1Q
21
2Q
20
3Q
19
4Q
18
5Q
17
6Q
16
7Q
15
8Q
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443


Part Number SN74BCT29846
Description 8-Bit Bus-Interface D-Type Latch
Maker Texas
Total Page 5 Pages
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