9ĆBIT BUSĆINTERFACE DĆTYPE LATCH
WITH 3ĆSTATE OUTPUTS
SCBS077A − SEPTEMBER 1991 − REVISED NOVEMBER 1993
• State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
The SN74BCT29844 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing wider buffer registers,
I/O ports, bidirectional bus drivers with parity, and
DW OR NT PACKAGE
The nine latches are transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs are
complementary to the inverting data (D) inputs.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
need for interface or pull-up components.
The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74BCT29844 is characterized for operation from 0°C to 70°C.
CLR OE LE
H L HH
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1993, Texas Instruments Incorporated
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