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SN74AS1843 Datasheet

9-Bit Bus Interface D-Type Latches

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SN74AS1843
9BIT BUS INTERFACE DTYPE LATCHES WITH 3STATE OUTPUTS
Center VCC and GND Configuration
Provides Minimum Lead Inductance in High
Current Switching Applications
3-State Buffer-Type Outputs Drive
Bus-Lines Directly
Bus-Structured Pinout
Provide Extra Bus Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
Buffered Control Inputs to Reduce DC
Loading
Power-Up High Impedance
Package Options Include Plastic DIPs. Use
the AS843 for Plastic and Ceramic Chip
Carriers and “Small Outline” Package
Options
Dependable Texas Instruments Quality and
Reliability
description
This 9-bit latch device features three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The nine latches are transparent D-type and have
noninverting data (D) inputs.
A buffered output control (OC) input can be used
to place the nine outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pullup components.
The output control (OC) does not affect the
internal operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are off.
The SN74AS1843 is characterized for operation
from 0°C to 70°C.
SDAS127 − APRIL 1987
NT Package
(Top View)
5Q
4Q
3Q
2Q
1Q
VCC
OC
1D
2D
3D
4D
5D
1
2
3
4
5
6
7
8
9
10
11
12
24 6Q
23 7Q
22 8Q
21 9Q
20 PRE
19 C
18 GND
17 CLR
16 9D
15 8D
14 7D
13 6D
PRE
L
H
H
H
H
X
FUNCTION TABLE
CLR
X
L
H
H
H
X
INPUTS
OC
L
L
L
L
L
H
C
X
X
H
H
L
X
D
X
X
L
H
X
X
OUTPUT
Q
H
L
L
H
QO
Z
logic symbol
7
OC
20
PRE
17
CLR
19
C
EN
S2
R
C1
1D 8
9
2D
10
3D
11
4D
12
5D
13
6D
14
7D
15
8D
16
9D
1D
2
5
1Q
4
2Q
3
3Q
2
4Q
1
5Q
24
6Q
23
7Q
22
8Q
21
9Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12,
PRODUCTION DATA information is current as of
publication date. Products conform to specifications
per the terms of Texas Instruments standard
warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 1987, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1


Texas Instruments (TI) Electronic Components Datasheet

SN74AS1843 Datasheet

9-Bit Bus Interface D-Type Latches

No Preview Available !

SN74AS1843
9BIT BUS INTERFACE DTYPE LATCHES WITH 3STATE OUTPUTS
SDAS127 − APRIL 1987
logic diagram (positive logic)
OC 7
PRE 20
CLR 17
C 19
8
1D
S
C1 5
1D 1Q
R
9
2D
S
C1 4
1D 2Q
R
S
10 C1 3
3D 1D 3Q
R
11
4D
S
C1 2
1D 4Q
R
S
12 C1 1
5D 1D 5Q
R
S
13 C1 24
6D 1D 6Q
R
S
14 C1 23
7D 1D 7Q
R
S
15 C1 22
8D 1D 8Q
R
S
16 C1 21
9D 1D 9Q
R
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN74AS1843
Description 9-Bit Bus Interface D-Type Latches
Maker Texas
Total Page 5 Pages
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