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Texas Instruments (TI) Electronic Components Datasheet

SN54BCT373 Datasheet

OCTAL TRANSPARENT D-TYPE LATCHES

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D Operating Voltage Range of 4.5 V to 5.5 V
D State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
D Full Parallel Access for Loading
SN54BCT373 . . . J OR W PACKAGE
SN74BCT373 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 LE
SN54BCT373, SN74BCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS016D – SEPTEMBER 1988 – REVISED MARCH 2003
D 3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
SN54BCT373 . . . FK PACKAGE
(TOP VIEW)
2D
3 2 1 20 19
4 18
8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’BCT373 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched
at the logic levels that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74BCT373N
SN74BCT373N
0°C to 70°C
SOIC – DW
Tube
Tape and reel
SN74BCT373DW
SN74BCT373DWR
BCT373
SOP – NS
Tape and reel SN74BCT373NSR
BCT373
SSOP – DB
Tape and reel SN74BCT373DBR
BT373
CDIP – J
Tube
SNJ54BCT373J
SNJ54BCT373J
–55°C to 125°C CFP – W
Tube
SNJ54BCT373W
SNJ54BCT373W
LCCC – FK
Tube
SNJ54BCT373FK
SNJ54BCT373FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1


Texas Instruments (TI) Electronic Components Datasheet

SN54BCT373 Datasheet

OCTAL TRANSPARENT D-TYPE LATCHES

No Preview Available !

SN54BCT373, SN74BCT373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS016D SEPTEMBER 1988 REVISED MARCH 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L HH
H
LHL
L
LLX
HXX
Q0
Z
logic diagram (positive logic)
OE 1
LE 11
3
1D
C1
1D
2 1Q
To Seven Other Channels
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN54BCT373
Description OCTAL TRANSPARENT D-TYPE LATCHES
Maker Texas
Total Page 17 Pages
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