SEP02G72E2BF2SA-30R Datasheet | Swissbit

Features : 240 Pin RDIMM SEP02G72E2BF2SA-30R 2GB PC2-5300 in FBGA Technology Ro HS pliant - - - - - - - - - - 240-pin 72-bit DDR2 registered Dual-In-Line Double Data Rate Synchronous DRAM Module for server applications Module organization: dual rank 256M x 72 VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V 1.8V I/O ( SSTL_18 patible) Serial Presence Detect with EEPROM Supports ECC error detection and correction JEDEC patible DDR2 PLL/Register ponent with parity bit support for address and control bus Gold-contact pad This module family is fully pin and functional patible to JEDEC. (see .jedec.org) The pcb and all ponents are manufactured according to the Ro HS pliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (Ro HS)] DDR2 SDRAM ponent Samsung K4T1G084QF 128Mx8 DDR2 SDRAM in FBGA-60 package Four bit prefetch architecture Programmable CAS latency (CL) Posted CAS additive latency (AL) WRITE latency = READ latency - 1 t CK Programmable burst length: 4 or 8 Adjustable...