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P8M648YL - (P8M648YLx / P8M6416YLEx) 8M/16M x 64 DIMM SDRAM Module

Download the P8M648YL datasheet PDF. This datasheet also covers the P8M648YLE variant, as both devices belong to the same (p8m648ylx / p8m6416ylex) 8m/16m x 64 dimm sdram module family and are provided as variant models within a single manufacturer datasheet.

Description

The P8M648YL, P8M648YLE, P16M6416YL, and P16M6416YLE are high performance dynamic randomaccess 64MB and 128MB modules respectively.

These modules are organized in a x64 configuration, and utilize quad bank architecture with a synchronous interface.

Features

  • P8M648YLE, P16M6416YLE 8M, 16M x 64 DIMM PC-100 and PC133 Compatible JEDEC.
  • Standard 168-pin , dual in-line memory Module (DIMM) TSOP components. Single 3.3v +.3v power supply. Nonbuffered fully synchronous; all signals measured on positive edge of system clock. Internal pipelined operation; column address can be changed every clock cycle. Quad internal banks for hiding row access/precharge. 64m.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (P8M648YLE_SpecTek.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number P8M648YL
Manufacturer SpecTek
File Size 64.41 KB
Description (P8M648YLx / P8M6416YLEx) 8M/16M x 64 DIMM SDRAM Module
Datasheet download datasheet P8M648YL Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
P8M648YL, P16M6416YL Preliminary Release V1 SDRAM MODULE Features: • • • • • • • • • P8M648YLE, P16M6416YLE 8M, 16M x 64 DIMM PC-100 and PC133 Compatible JEDEC – Standard 168-pin , dual in-line memory Module (DIMM) TSOP components. Single 3.3v +.3v power supply. Nonbuffered fully synchronous; all signals measured on positive edge of system clock. Internal pipelined operation; column address can be changed every clock cycle. Quad internal banks for hiding row access/precharge. 64ms 4096 cycle refresh. All inputs, outputs, clocks LVTTL compatible.
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