P8M646YLG, P16M6412YLG
CAPACITANCE: (This parameter is sampled. VCC = +3.3V ± 0.3V; f = 1 MHz)
Parameter
Symbol
Input Capacitance: A0 - A11, BAO, BA1, RAS#, CAS#, WE#,
CKE0,CKE1
Input Capacitance: CK0-CK3
Input Capacitance: S0#- S3#
Input Capacitance: DQMB0#, DQMB7#
Input Capacitance: SCL, SA0-SA2, SDA
Input/Output Capacitance: DQ0-DQ63
Cl1
Cl2
Cl3
Cl4
Cl01
CIO2
Max
64MB 128MB
25 50
25 25
12 12
6 10
10 10
8 14
Units
pF
pF
pF
pF
pF
pF
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS:
Parameter
Symbol
Min
Supply Voltage
Vcc/Vccq
3.0
Input High (Logic 1) Voltage, All inputs
Input Low (Logic 0) Voltage, All inputs
Input Leakage Current Any input = 0V < VIN < Vcc
All other pins not under test = 0V
Output Leakage Current DQs are disabled; 0V < VOUT < VccQ
Output High Voltage (IOUT = -4 mA)
Output Low Voltage (IOUT = 4 mA)
VIH 2.0
VIL -0.3
II -10
I2 -20
I3 -30
IOZ -10
VOH 2.4
VOL
Max
3.6
Vcc + .3
0.8
10
20
30
10
0.4
Units
V
V
V
uA
uA
uA
uA
V
V
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS: Vcc = 3.3V ± 10%V, Temp. = 25° to 70 °C
Supply Current
Symbol
SIZE -75A -8A Units Notes
OPERATING CURRENT: ACTIVE mode, burst
= 2, READ or WRITE, tRC = tRC (MIN), one
bank active,
CL= 2
CL = 3
Icc1
64MB N/A N/A
mA
128MB N/A N/A
Icc1
64MB 990 840
mA 1, 2, 3
128MB 1980 1680
STANDBY CURRENT: POWER-DOWN mode, CKL = LOW
CKE = LOW, no accesses in progress
Icc2
64MB
12
12
mA
128MB 24
24
STANDBY CURRENT: Active Mode
CS# = HIGH, CKE = HIGH, all banks active after tRCD met, no
accesses in progress.
Icc3
64MB 300 240
mA
3, 4
128MB 600 480
OPERATING CURRENT: BURST Mode;
Continuous burst; READ or WRITE; all banks
active
CL= 2
CL = 3
Icc4
64MB N/A N/A
mA 1, 2, 3
128MB N/A N/A
Icc4
64MB 900 840
mA 1, 2, 3
128MB 1800 1680
AUTO REFRESH CURRENT tRC = tRC (MIN)
Icc6 64MB 1860 1620 mA 1, 2, 3
128MB 3720 3240
NOTES:
1. Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the
outputs open.
2. The Icc current will decrease as the CAS latency is reduced. This is because maximum cycle rate is slower as CAS
latency is reduced.
3. Address transitions average one transition every 30ns.
4. Other input signals are allowed to transition no more than once in any 30ns period.
__________________________________________________________________________________________________
P8M646YLG, P16M6412YLG
2 SpecTek reserves the right to change products
or specifications without notice. 1999 SpecTek
Rev: 5/17/01
