P4M644YL, P8M648YL
CAPACITANCE: (This parameter is sampled. VCC = +3.3V m 0.3V; f = 1 MHz)
Parameter
Symbol
Input Capacitance: A0 - A11, BAO-BA1, RAS#, CAS#, WE#,
Input Capacitance: S0#-S3#, CK0-CK3
Input Capacitance: CKE0, CKE1,
Input Capacitance: DQMB0#, DQMB7
Input Capacitance: SQL, SA0-SA2
Input/Output Capacitance: DQ0-DQ63, SDA
Cl1
Cl2
Cl3
Cl4
Cl5
CIO
Max
32MB 64MB
25 45
15 25
25 45
8 15
66
10 15
Units
pF
pF
pF
pF
pF
pF
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS:
Parameter
Symbol
Min
Supply Voltage
Vcc/Vccq
3.0
Input High (Logic 1) Voltage, All inputs
Input Low (Logic 0) Voltage, All inputs
Input Leakage Current Any input = 0V < VIN < Vcc
All other pins not under test = 0V
Output Leakage Current DQs are disabled; 0V < VOUT < VccQ
Output High Voltage (IOUT = -4 mA)
Output Low Voltage (IOUT = 4 mA)
VIH 2.0
VIL -0.3
II -10
I2 -20
I3 -30
IOZ -20
VOH 2.4
VOL
Max
3.6
Vcc + .3
0.8
10
20
30
20
0.4
Units
V
V
V
uA
uA
V
V
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS: Vcc = 3.3V ± 10%V, Temp. = 25° to 70 °C
Supply Current
Symbol
-8A -10 Units Notes
OPERATING CURRENT: ACTIVE mode, burst =
1, READ or WRITE, tRC > tRC (MIN), one bank
active,
CL = 2
CL = 3
Icc1 32MB N/A 380 mA 1, 2, 3
64MB
730
Icc1
32MB
440
420 mA 1, 2, 3
64MB
890
850
STANDBY CURRENT: POWER-DOWN mode,
CKE = LOW, no accesses in progress
tCK = 15ns
CLK = LOW
Icc2 32MB 20
64MB
40
Icc2 32MB 20
64MB
40
16 mA
32
8 mA
16
STANDBY CURRENT: CS# = HIGH, CKE = HIGH,
tCK = 15ns, both banks idle
Icc3
32MB
200
64MB
400
200 mA 3, 4
400
STANDBY CURRENT: CS# = HIGH, CKE = HIGH, tCK = 15ns,
both banks active after tRCD met, no accesses in progress.
Icc4
32MB
200
64MB
400
200 mA 3, 4
400
OPERATING CURRENT: BURST mode after tRCD
met, continuous burst, READ, WRITE, tCK > tCK. MIN,
other bank active
CL = 2
CL = 3
Icc5 32MB N/A 680 mA 1, 2, 3
64MB
880
Icc5
32MB
780
740 mA 1, 2, 3
64MB
980
960
AUTO REFRESH CURRENT tRC > tRC (MIN)
CL = 2
CL = 3
Icc6 32MB6 N/A 780 mA 1, 2, 3
4MB
1560
Icc6 32MB 1000 960 mA 1, 2, 3
64MB
2000
1920
NOTES:
1. Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
2. The Icc current will decrease as the CAS latency is reduced. This is because maximum cycle rate is slower as CAS latency is
reduced.
3. Address transitions average one transition every 30ns.
4. Other input signals are allowed to transition no more than once in any 30ns period.
__________________________________________________________________________________________________
P4M644
2 SpecTek reserves the right to change products
Rev: 6/14/99
or specifications without notice. ©1999 SpecTek
