Description
of Spansion data sheet designations are presented here to highlight their presence and definitions..
Features
- S CPU Core
32-bit RISC, load/store architecture, 5-stage pipeline Maximum operating frequency:
MB91F52xR/MB91F52xU(LQFP): 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied (PLL clock multiplication system))
MB91F52xR/MB91F52xU(TEQFP): 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied (PLL clock multiplication system))
MB91F52xM/ MB91F52xY: 128 MHz (Source oscillation = 4.0 MHz and 32 multiplied (PLL clock multiplication system))
General-purpose register : 32-bit ×16 sets 16-bi.
