CMOS High Voltage Logic – CD4093B
Quadruple 2-Input NAND Gate Logic IC with Schmitt-Trigger Inputs in bare die form
Rev 1.0
21/11/17
Description
Features:
The CD4093B Quad 2-Input NAND Gate is fabricated
using a 3µm 15CMOS process. This device consists of
x4 Schmitt-trigger circuits. Each circuit functions as a
2-input NAND gate with Schmitt trigger action on both
inputs. The gate switches at different points for positive
& negative-going signals. The difference between the
positive (VT+) & the negative voltage (VT−) is defined
as hysteresis voltage (VH). Device hysteresis
characteris tics transform slowly changing input signals
into sharply defined jitter-free output signals.
High Input Voltage up to 20V
Schmitt-trigger on each input
No limit on input rise and fall time
Noise immunity greater than 50%
Drives x2 Low-Power TTL loads or x1 LSTTL load
Symmetrical Sink & Source Currents
Direct drop-in replacement for obsolete
components in long term programs.
Ordering Information
Die Dimensions in µm (mils)
The following part suffixes apply:
No suffix - MIL-STD-883 /2010B Visual Inspection
“H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
“K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
1560 (61)
Supply Formats:
Default – Die in Waffle Pack (400 per tray capacity)
Sawn Wafer on Tape – On request
Unsawn Wafer – On request
Die Thickness <> 350µm(15 Mils) – On request
Assembled into Ceramic Package – On request
Mechanical Specification
Die Size (Unsawn)
Minimum Bond Pad Size
Die Thickness
Top Metal Composition
Back Metal Composition
1560 x 1120
61 x 44
µm
mils
100 x 100
3.94 x 3.94
µm
mils
350 (±20)
13.78 (±0.79)
µm
mils
Al 1%Si 1.1µm
N/A – Bare Si
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