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CD4093B Datasheet Preview

CD4093B Datasheet

Quadruple 2-Input NAND Gate Logic IC

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CMOS High Voltage Logic – CD4093B
Quadruple 2-Input NAND Gate Logic IC with Schmitt-Trigger Inputs in bare die form
Rev 1.0
21/11/17
Description
Features:
The CD4093B Quad 2-Input NAND Gate is fabricated
using a 3µm 15CMOS process. This device consists of
x4 Schmitt-trigger circuits. Each circuit functions as a
2-input NAND gate with Schmitt trigger action on both
inputs. The gate switches at different points for positive
& negative-going signals. The difference between the
positive (VT+) & the negative voltage (VT−) is defined
as hysteresis voltage (VH). Device hysteresis
characteris tics transform slowly changing input signals
into sharply defined jitter-free output signals.
ƒ High Input Voltage up to 20V
ƒ Schmitt-trigger on each input
ƒ No limit on input rise and fall time
ƒ Noise immunity greater than 50%
ƒ Drives x2 Low-Power TTL loads or x1 LSTTL load
ƒ Symmetrical Sink & Source Currents
ƒ Direct drop-in replacement for obsolete
components in long term programs.
Ordering Information
Die Dimensions in µm (mils)
The following part suffixes apply:
ƒ No suffix - MIL-STD-883 /2010B Visual Inspection
ƒ H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
ƒ K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
1560 (61)
Supply Formats:
ƒ Default – Die in Waffle Pack (400 per tray capacity)
ƒ Sawn Wafer on Tape – On request
ƒ Unsawn Wafer – On request
ƒ Die Thickness <> 350µm(15 Mils) – On request
ƒ Assembled into Ceramic Package – On request
Mechanical Specification
Die Size (Unsawn)
Minimum Bond Pad Size
Die Thickness
Top Metal Composition
Back Metal Composition
1560 x 1120
61 x 44
µm
mils
100 x 100
3.94 x 3.94
µm
mils
350 (±20)
13.78 (±0.79)
µm
mils
Al 1%Si 1.1µm
N/A – Bare Si
Page 1 of 6
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CD4093B Datasheet Preview

CD4093B Datasheet

Quadruple 2-Input NAND Gate Logic IC

No Preview Available !

CMOS High Voltage Logic – CD4093B
d
Pad Layout and Functions
Rev 1.0
21/11/17
12
13
14
1
2
11 10
9
8
DIE ID
7
34
6
5
0,0
1560µm (61.42 mils)
Logic Diagram
PAD
FUNCTION
COORDINATES (mm)
XY
1
A1
0.1135
0.3290
2
B1
0.2005
0.1130
3
Y1
0.5865
0.1130
4
Y2
0.8305
0.1130
5
A2
1.1235
0.1130
6
B2
1.3460
0.1975
7
VSS
1.2765
0.4280
8
A3
1.3460
0.6910
9
B3
1.2595
0.9070
10
Y3
0.8735
0.9070
11
Y4
0.6295
0.9070
12
A4
0.3365
0.9070
13
B4
0.1140
0.8225
14
VDD
0.1135
0.5595
CONNECT CHIP BACK TO VDD OR FLOAT
Truth Table
INPUTS
AB
OUTPUT
Y
LL
LH
HL
HH
H
H
H
L
H = High level (steady state)
L = Low level (steady state)
Page 2 of 6
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Part Number CD4093B
Description Quadruple 2-Input NAND Gate Logic IC
Maker Silicon Supplies
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