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CD4049B Datasheet Preview

CD4049B Datasheet

Hex Inverter / Buffer Logic

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CMOS High Voltage Logic – CD4049B
Hex Inverter / Buffer Logic IC in bare die form
Rev 1.0
21/11/17
Description
Features:
The CD4049B Inverting Hex Buffer is fabricated on a
3µm 15CMOS process. The device is typically used as
a Hex Buffer, CMOS to TTL converter or as a CMOS
current driver. Logic levels are converted using only
one supply voltage (VDD). Special input protection
allows the input signal high level (VIH) to exceed the
VDD supply voltage when the device is used for logic
level conversion. Two TTL/DTL loads can be driven
over the full temperature range when the devices are
used as lev el converters.
ƒ High Input Voltage up to 20V
ƒ Inputs allow voltages greater than VDD
ƒ High Source and Sink Currents
ƒ x2 TTL load drive over Military Temperature range
ƒ Specified at 5V, 10V & 15V
ƒ Direct drop-in replacement for obsolete
components in long term programs.
Ordering Information
Die Dimensions in µm (mils)
The following part suffixes apply:
ƒ No suffix - MIL-STD-883 /2010B Visual Inspection
ƒ H” - MIL-STD-883 /2010B Visual Inspection
+ MIL-PRF-38534 Class H LAT
ƒ K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL-PRF-38534 Class K LAT
LAT = Lot Acceptance Test.
For further information on LAT process flows see below.
www.siliconsupplies.com\quality\bare-die-lot-qualification
1550 (61)
Supply Formats:
ƒ Default – Die in Waffle Pack (100 per tray capacity)
ƒ Sawn Wafer on Tape – On request
ƒ Unsawn Wafer – On request
ƒ Die Thickness <> 350µm(15 Mils) – On request
ƒ Assembled into Ceramic Package – On request
Mechanical Specification
Die Size (Unsawn)
Minimum Bond Pad Size
Die Thickness
Top Metal Composition
Back Metal Composition
1550 x 1500
61 x 59
µm
mils
106 x 106
4.17 x 4.17
µm
mils
350 (±20)
13.78 (±0.79)
µm
mils
Al 1%Si 1.1µm
N/A – Bare Si
Page 1 of 5
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Silicon Supplies

CD4049B Datasheet Preview

CD4049B Datasheet

Hex Inverter / Buffer Logic

No Preview Available !

CMOS High Voltage Logic – CD4049B
Pad Layout and Functions
Rev 1.0
21/11/17
13 12 11 10
9
14
1
2
3
0,0
8
DIE ID
7
4 56
1550µm (61.02 mils)
Logic Diagram
PAD
FUNCTION
COORDINATES (mm)
XY
1
VDD
0.110
0.505
2
1Y
0.110
0.305
3
1A
0.110
0.110
4
2Y
0.542
0.110
5
2A
0.982
0.110
6
3Y
1.320
0.110
7
3A
1.320
0.280
8
VSS
1.320
0.700
9
4A
1.320
1.090
10
4Y
1.320
1.270
11
5A
0.942
1.270
12
5Y
0.542
1.270
13
6A
0.110
1.270
14
6Y
0.110
1.020
CONNECT CHIP BACK TO VDD OR FLOAT
Truth Table
INPUTS
A
OUTPUT
Y
HL
LH
H = High level (steady state)
L = Low level (steady state)
PAD 1 = VDD
PAD 8 = VSS
Page 2 of 5
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Part Number CD4049B
Description Hex Inverter / Buffer Logic
Maker Silicon Supplies
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CD4049B Datasheet PDF






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