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54HC112 Datasheet Preview

54HC112 Datasheet

Dual J-K Flip-Flops

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R   High Speed CMOS Logic  54HC112
 
Dual J-K  Flip-Flops with preset and clear; negative edge trigger in bare die form
Rev 1.0
24/11/17
Descrip  tion
Features:
The 54HC1 12 is fabricated using a 2.5µm 5V CMOS
process and has the same high speed performance of
LSTTL com  bined with CMOS low power consumption.
Each flip-flop has independent J, K, preset, clear, clock
inputs and  Q Q outputs. A high level at the clock input
enables the J and K inputs to accept data. The device
changes st ate on the negative going transition of the clock
pulse. Preset and clear are independent of the clock and
are accomp  lished by a low logic level on the corresponding
input. Schmitt-trigger action in the clock input makes the
circuit highl y tolerant to slower clock rise and fall times. 
ƒ Output Drive Capability: 10 LSTTL Loads
ƒ Bus Drive Capability: 15 LSTTL Loads
ƒ Low Input Current: 1µA
ƒ Outputs directly interface CMOS, NMOS and TTL
ƒ Operating Voltage Range: 2V to 6V
ƒ CMOS High Noise Immunity
ƒ Function compatible with 54LS112
ƒ Full Military Temperature Range.
 
Ordering Information
 
The following part suffixes apply:
ƒ No suf fix - MIL-STD-883 /2010B Visual Inspection
ƒ H” - M IL-STD-883 /2010B Visual Inspection
  + MIL-PRF-38534 Class H LAT
ƒ K” - MIL-STD-883 /2010A Visual Inspection (Space)
  + MIL-PRF-38534 Class K LAT
Die Dimensions in µm (mils)
1500 (59)
LAT = Lot  Acceptance Test.
For further information on LAT process flows see below.
www.silico nsupplies.com\quality\bare-die-lot-qualification
Supply  Formats:
 
ƒ Default – Die in Waffle Pack (100 per tray capacity)
ƒ Sawn W  afer on Tape – On request
ƒ Unsaw n Wafer – On request
ƒ Die Thi ckness <> 350µm(14 Mils) – On request
ƒ Assem bled into Ceramic Package – On request
Mechanical Specification
Die Size (Unsawn)
Minimum Bond Pad Size
Die Thickness
Top Metal Composition
Back Metal Composition
1500 x 1700
59 x 67
µm
mils
120 x 120
4.72 x 4.72
µm
mils
350 (±20)
13.78 (±0.79)
µm
mils
Al 1%Si 1.1µm
N/A – Bare Si
Page 1 of 6 
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Silicon Supplies

54HC112 Datasheet Preview

54HC112 Datasheet

Dual J-K Flip-Flops

No Preview Available !

  High Speed CMOS Logic  54HC112
d 
Pad La  yout and Functions
 
  14
 
 
 
15
 
  16
 
 1
 2
13
 
12
DIE ID
11
10
9
8
7
34
56
 
0,0
 
 
1500µm (59.06 mils)
Truth  Table
  INPUTS
PRE
CLR
CLK
J
K
L 
H
X XX
OUTPUTS
QQ
HL
H
 
L
L
L
X XX L
H
X X X H* H*
H 
H
H 
H
H
H
↓ L L NO CHANGE
↓ HL H
L
LH
L
H
H 
H
H
H
↓ HH
TOGGLE
H X X NO CHANGE
H = High level (steady state), L = Low level (steady state)
X = Don’t care, ↓ = High-to-Low transition
* O utput states unpredictable if both PRE and CLR go High
simultaneously after both being low at the same time.
Rev 1.0
24/11/17
PAD
FUNCTION
COORDINATES (mm)
XY
1
1CLK
0.125
0.345
2
1K
0.135
0.125
3
1J
0.585
0.135
4
1PRE
0.755
0.135
5
1Q
1.025
0.135
6
1Q
1.225
0.135
7
2Q
1.245
0.54
8
GND
1.245
0.735
9 2Q
1.26
0.995
10 2PRE
1.26
1.165
11 2J
1.25
1.47
12 2K
0.86
1.48
13 2CLK
0.48
1.48
14 2CLR
0.125
1.47
15 1CLR
0.125
0.855
16 VCC
0.125
0.615
CONNECT CHIP BACK TO VCC OR FLOAT
Logic Diagram
x1 Flip-Flop
Page 2 of 6 
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Part Number 54HC112
Description Dual J-K Flip-Flops
Maker Silicon Supplies
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