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SST32HF32A2 Datasheet Preview

SST32HF32A2 Datasheet

Multi-Purpose Flash Plus PSRAM ComboMemory

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Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF32A2
FEATURES:
SST32HF32A32Mb Flash + 16Mb SRAM
(x16) MCP ComboMemories
Preliminary Specifications
• ComboMemories organized as:
– 2M x16 Flash + 1024K x16 PSRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or Write to PSRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or PSRAM Read
– Standby Current: 60 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Erase-Suspend/Erase-Resume Capabilities
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST32HF32A2
• Fast Read Access Times:
– Flash: 70 ns
– PSRAM: 70 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Flash Automatic Erase and Program Timing
– Internal VPP Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 63-ball LFBGA (8mm x 10mm x 1.4mm)
– 62-ball LFBGA (8mm x 10mm x 1.4mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
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The SST32HF32A2 ComboMemory devices integrate a
CMOS flash memory bank with a CMOS PseudoSRAM
(PSRAM) memory bank in a Multi-Chip Package (MCP),
manufactured with SST’s proprietary, high-performance
SuperFlash technology.
Featuring high-performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. To protect against inadvertent flash write, the
SST32HF32A2 devices contain on-chip hardware and soft-
ware data protection schemes. The SST32HF32A2
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HF32A2 devices consist of two independent
memory banks with respective bank enable signals. The
flash and PSRAM memory banks are superimposed in the
same memory address space. Both memory banks share
common address lines, data lines, WE# and OE#. The
memory bank selection is done by memory bank enable
signals. The PSRAM bank enable signal, BES# selects the
PSRAM bank. The flash memory bank enable signal,
BEF# selects the flash memory bank. The WE# signal has
to be used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST32HF32A2 provide the added functionality of
being able to simultaneously read from or write to the
PSRAM bank while erasing or programming in the flash
memory bank. The PSRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the PSRAM
bank can be accessed for Read or Write.
©2005 Silicon Storage Technology, Inc.
S71261-01-000
5/05
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.




Silicon Storage Technology

SST32HF32A2 Datasheet Preview

SST32HF32A2 Datasheet

Multi-Purpose Flash Plus PSRAM ComboMemory

No Preview Available !

Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF32A2
Preliminary Specifications
The SST32HF32A2 devices are suited for applications that
use both flash memory and PSRAM memory to store code
or data. For systems requiring low power and small form
factor, the SST32HF32A2 devices significantly improve
performance and reliability, while lowering power consump-
tion, when compared with multiple chip solutions. The
SST32HF32A2 inherently use less energy during erase
and program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
Device Operation
The SST32HF32A2 use BES1#, BES2 and BEF# to con-
trol operation of either the flash or the PSRAM memory
bank. When BEF# is low, the flash bank is activated for
Read, Program or Erase operation. When BES1# is low,
and BES2 is high the PSRAM is activated for Read and
Write operation. BEF# and BES1# cannot be at low level,
and BES2 cannot be at high level at the same time. If all
www.DabtanShkeetn4aUb.cloemsignals are asserted, bus contention will
result and the device may suffer permanent damage.
All address, data, and control lines are shared by flash and
PSRAM memory banks which minimizes power consump-
tion and loading. The device goes into standby when BEF#
and BES1# bank enables are raised to VIHC (Logic High) or
when BEF# is high and BES2 is low.
Concurrent Read/Write Operation
The SST32HF32A2 provide the unique benefit of being
able to read from or write to PSRAM, while simultaneously
erasing or programming the flash. This allows data alter-
ation code to be executed from PSRAM, while altering the
data in flash. See Figure 26 for a flowchart. The following
table lists all valid states.
CONCURRENT READ/WRITE STATE TABLE
Flash
Program/Erase
Program/Erase
PSRAM
Read
Write
The device will ignore all SDP commands when an Erase
or Program operation is in progress. Note that Product
Identification commands use SDP; therefore, these com-
mands will also be ignored while an Erase or Program
operation is in progress.
Flash Read Operation
The Read operation of the SST32HF32A2 devices is con-
trolled by BEF# and OE#. Both have to be low, with WE#
high, for the system to obtain data from the outputs. BEF#
is used for flash memory bank selection. When BEF# is
high, the chip is deselected and only standby power is
consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when OE# is high. Refer to Figure 6 for further
details.
©2005 Silicon Storage Technology, Inc.
2
S71261-01-000
5/05


Part Number SST32HF32A2
Description Multi-Purpose Flash Plus PSRAM ComboMemory
Maker Silicon Storage Technology
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