SI5335 Datasheet | Silicon Labs

WEB- C USTOMIZABLE, A NY- F REQUENCY, A NY- O UTPUT QUAD CLOCK GENERATOR/BUFFER Features - Low power Multi Synth™ technology - Independent output voltage per driver: enables independent, any-frequency 1.5, 1.8, 2.5, or 3.3 V synthesis of four frequencies - Single supply core with excellent - Configurable as a clock generator or PSRR: 1.8, 2.5, 3.3 V clock buffer device - Up to five user-assignable pin - Three independent, user-assignable, pin- functions simplify system design: selectable device configurations SSENB (spread spectrum control), - Highly-configurable output drivers with RESET, Master OEB or OEB per pin, up to four differential outputs, eight and Frequency plan select single-ended clock outputs, or a (FS1, FS0) bination of both - Loss of signal alarm - Low phase jitter of 0.7 ps RMS - PCIe Gen 1/2/3/4 mon clock - Flexible input reference: pliant - External crystal: 25 or 27 MHz - PCIe Gen 3 SRNS pliant - CMOS input: 10 to 200 MHz - Two selectable loop bandwidth - SSTL/HSTL input: 10 to 350 MHz settings: 1.6 MHz or 475 k Hz - Differential input: 10 to 350 MHz - Independently configurable outputs support any frequency or format: - LVPECL/LVDS/CML: 1 to 350 MHz - HCSL: 1 to 250 MHz - CMOS: 1 to 200 MHz - SSTL/HSTL: 1 to 350 MHz - Easy to customize with web-based...