SI53156 Datasheet | Silicon Labs

PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER Features - PCI-Express Gen 1, Gen 2, Gen 3, - Six PCI-Express buffered clock and Gen 4 mon clock pliant outputs - Supports Serial ATA (SATA) at - Clock input spread tolerable 100 MHz - Supports LVDS outputs - 100- 210 MHz operation - I2C support with readback - Low power, push pull, differential capabilities output buffers - Extended temperature: - - Internal termination for maximum integration - Dedicated output output enable pin for each - - 40 to 85 o C 3.3 V power supply 32-pin QFN package Applications - Network attached storage - Multi-function printers - Wireless access point - Routers Description The Si53156 is a spread spectrum tolerant PCIe clock buffer that can source six PCIe clocks simultaneously. The device has six hardware output enable control inputs for enabling the respective differential outputs on the fly. The device also Features output enable control through I2C munication. I2C programmability is also available to dynamically control skew, edge rate and amplitude on the true, pliment, or both differential signals on the clock outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at .silabs./pcie-learningcenter. Functional Block Diagram Ordering Information: See page 17. Pin Assignments OE1- OE0- DIFFIN DIFFIN VDD CKPWRGD_PDB- SDATA SCLK 32 31 30 29 28 27 26 25 VDD 1 24...