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Silego

SLG74190 Datasheet Preview

SLG74190 Datasheet

1 to 19 Differential Clock Buffer

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Features
• Intel DB1900Z Clock Specification Revision 1.0
• 1:19 Differential Zero Delay Buffer
• PCIe Gen 2/Gen3 & Intel ® QPI
• 100ps Input to Output Delay
• HCSL Output Buffer
• Configuration PLL (ZDB) and Bypass Mode
• Programmable PLL Bandwidth
• 72 pin QFN package (6/6 RoHS Compliant)
SLG74190
1 to 19
Differential Clock Buffer
Output Summary
• 19 - differential clock output pairs @ 0.7V
• 8 - OE# input pins to control output
• 1 - differential external feedback output pair
SMBus Address Table
SA_1
L
L
L
M
M
M
H
H
H
SA_0
L
M
H
L
M
H
L
M
H
SMBus
Address
D8
DA
DE
C2
C4
C6
CA
CC
CE
Note: SA_1 & SA_0 have an integrated
pull-down resistor @100kΩ
Pin Configuration
(Top View)
VDDA
GNDA
IREF
*100M_133M#
HBW_BYPASS_LBW#
PWRGD/PWRDN#
GND
VDD
CLK_IN
CLK_IN#
^SA_0
SDA
SCL
^SA_1
FB_IN
FB_IN#
FB_OUT#
FB_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SLG74190
54 OE_11#
53 DIF_11#
52 DIF_11
51 OE_10#
50 DIF_10#
49 DIF_10
48 OE_9#
47 DIF_9#
46 DIF_9
45 VDD
44 GND
43 OE_8#
42 DIF_8#
41 DIF_8
40 OE_7#
39 DIF_7#
38 DIF_7
37 OE_6#
72-Pin QFN
Note: Signals with “*” have internal pull-up resistors
Signals with “^” have internal pull-down resistors
Silego Technology, Inc.
000-0074190-102
Rev 1.02
Revised March 30, 2016




Silego

SLG74190 Datasheet Preview

SLG74190 Datasheet

1 to 19 Differential Clock Buffer

No Preview Available !

SLG74190
Pin Description
Pin # Name
1 VDDA
2 GNDA
3 IREF
4 100M_133M#
5 HBW_BYPASS_LBW#
6 PWRGD/PWRDN#
7 GND
8 VDD
9 CLK_IN
10 CLK_IN#
11 SA_0
12 SDA
13 SCL
14 SA_1
15 FB_IN
16 FB_IN#
17 FB_OUT#
18 FB_OUT
19 DIF_0
20 DIF_0#
21 VDD
22 DIF_1
23 DIF_1#
24 DIF_2
25 DIF_2#
26 GND
27 DIF_3
28 DIF_3#
29 DIF_4
Type
PWR
GND
I
I
I
I
GND
PWR
I
I
I
I/O, SE
I
I
I
I
O, DIF
O, DIF
O, DIF
O, DIF
PWR
O, DIF
O, DIF
O, DIF
O, DIF
GND
O, DIF
O, DIF
O, DIF
Description
3.3V Power supply for PLL
Ground for PLL
A precision resistor is attached to this pin to set the differential output current.
Use 475Ω , 1% for 100Ω trace.
Use 412Ω, 1% for 85Ω trace.
3.3V tolerant input for input/output frequency selection. An external pull-up or
pull-down resistor is attached to this pin to select the input/output frequency.
Contains internal weak pull-up 100kΩ resistor.
High = 100MHz output.
Low = 133MHz output.
Tri-Level input for selecting the PLL bandwidth or bypass mode (refer to trilevel
threshold table).
High = High BW mode
Med = Bypass mode
Low = Low BW mode
3.3 V LVTTL input to power up or power down the device.
Ground for outputs.
3.3V power supply for outputs.
0.7V Differential Input.
0.7V Differential Input.
3.3 V LVTTL input selecting the address. Tri-level input (refer to tri-level thresh-
old table).
Open collector SMBus data.
SMBus slave clock input.
3.3 V LVTTL input selecting the address. Tri-level input (refer to tri-level thresh-
old table).
External Feedback input.
External Feedback input. Complement.
External Feedback output.
External Feedback output. Complement.
0.7V Differential clock output.
0.7V Differential clock output.
3.3V power supply for outputs.
0.7V Differential clock output.
0.7V Differential clock output.
0.7V Differential clock output.
0.7V Differential clock output.
Ground for outputs.
0.7V Differential clock output.
0.7V Differential clock output.
0.7V Differential clock output.
000-0074190-102
Page 2 of 21


Part Number SLG74190
Description 1 to 19 Differential Clock Buffer
Maker Silego
Total Page 21 Pages
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