Download the 54S301 datasheet PDF. This datasheet also covers the 54S200 variant, as both devices belong to the same ttl 256 x 1 ram family and are provided as variant models within a single manufacturer datasheet.
The 54/74S200/201 and 54/74S301 are Schottky clamped TTL, read/write memory arrays organized as 256 words of one bit each.
They feature either open collector or tri-state outputs options for optimization of word expansion in bussed organizations.
| Part number | 54S301 |
|---|---|
| Manufacturer | Signetics |
| File Size | 194.58 KB |
| Description | TTL 256 x 1 RAM |
| Datasheet |
 54S301 Datasheet
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| Part Number | Description | Manufacturer |
|---|---|---|
| 54S32 | Quadruple 2-Input Positive-OR Gates | Texas Instruments |
| 54S04 | HEX INVERTING GATES | National Semiconductor |
| 54S08 | Quad 2-Input AND Gates | National Semiconductor |
| 54S08 | Quadruple 2-Input Positive-AND Gates | Texas Instruments |
| 54S10 | STTL type three 3-input NAND gate | TW |
| Part Number | Description |
|---|---|
| 54S189 | 64-Bit Bipolar Scratch Pad Memory |
| 54S200 | TTL 256 x 1 RAM |
| 54S201 | TTL 256 x 1 RAM |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.
