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SDA2546-5 - Nonvolatile Memory 4-Kbit E2PROM

General Description

I2C Bus Interface The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.

It consists of a data line SDA and a clock line SCL.

The data line requires an external pull-up resistor to VCC (open drain output stages).

Key Features

  • q Word-organized reprogrammable nonvolatile memory q q q q q q q q in n-channel floating-gate technology (E2PROM) 512 × 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/write cycle Reprogramming by means of on-chip control (without external control) The end of the programming cycle can be checked Data retention in excess of 10 years More than 104 reprogramming cycles per address P-DIP-8-1 Type SDA 2546-5 Ordering Code.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface SDA 2546-5 Preliminary Data MOS IC Features q Word-organized reprogrammable nonvolatile memory q q q q q q q q in n-channel floating-gate technology (E2PROM) 512 × 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/write cycle Reprogramming by means of on-chip control (without external control) The end of the programming cycle can be checked Data retention in excess of 10 years More than 104 reprogramming cycles per address P-DIP-8-1 Type SDA 2546-5 Ordering Code Q67100-H5096 Package P-DIP-8-1 Circuit Description I2C Bus Interface The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.