LH52D1000 Datasheet | Sharp Corporation

FEATURES - Access time: 85 ns (MAX.), 100 ns (MAX.) - Current consumption: Operating: 40 m A (MAX.) 6 m A (MAX.) (t RC, t WC = 1 µs) Standby: 45 µA (MAX.) - Data Retention: 1.0 µA (MAX. VCCDR = 3 V, t A = 25 °C) - Single power supply: 2.7 V to 3.6 V - Operating temperature: -40°C to +85°C - Fully-static operation - Three-state output - Not designed or rated as radiation hardened - Packages: 32-pin 8 × 20 mm2 TSOP 32-pin 8 × 13.4 mm2 STSOP - N-type bulk silicon DESCRIPTION The LH52D1000 is a static RAM organized as 131,072 × 8 bits which provides low-power standby mode. It is fabricated using silicon-gate CMOS process technology. A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 CMOS 1M (128K × 8) Static Ram PIN CONNECTIONS 32-PIN TSOP 32-PIN STSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TOP VIEW 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 52D1000S-1 Figure 1. Pin Connections for TSOP and STSOP Packages CMOS 1M (128K × 8) Static RAM 17 A4 16 A5 15 A6 14 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 13 3 2 31 1 12 4 11 7 10 ADDRESS BUFFER A0 A1 A2 A3 20 19 18 10 1024 ROW DECODER MEMORY CELL ARRAY (1024 x 128 x 8) 8 VCC 24 GND 128 x 8 7 COLUMN DECODER 128 COLUMN GATE 8 CE CONTROL LOGIC CE1 30 CE2 6 WE 5 OE 32 OE, WE CONTROL LOGIC I/O BUFFER 21 22 23 25 26 27 28 29 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 52D1000S-2 Figure 2. LH52D1000 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A0 - A16 CE1 CE2 WE OE Address inputs Chip enable 1 Chip enable 2 Write enable Output...