K7K1618T2C sram equivalent, 512kx36 & 1mx18 ddrii cio b2 sram.
* 1.8V+0.1V/-0.1V Power Supply.
* DLL circuitry for wide output data valid window and future freguency scaling.
* I/O Supply Voltage 1.5V+0.1V/-0.1V
* Pip.
where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, .
Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined when low Block Write Control Pin,active when low Inpu.
Image gallery
TAGS
Download