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K7B321835C - 1Mx36 & 2Mx18 Synchronous SRAM

Datasheet Summary

Description

The K7B323635C and K7B321835C are 37,748,736-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Features

  • Synchronous Operation.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • VDD= 2.5 or 3.3V +/- 5% Power Supply.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • Power Down State via ZZ Signal.
  • LBO Pin allows a choice of either a interleaved burst or a linear burst.
  • Three Chip Enables for.

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Datasheet preview – K7B321835C

Datasheet Details

Part number K7B321835C
Manufacturer Samsung semiconductor
File Size 477.15 KB
Description 1Mx36 & 2Mx18 Synchronous SRAM
Datasheet download datasheet K7B321835C Datasheet
Additional preview pages of the K7B321835C datasheet.

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Full PDF Text Transcription

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K7B323635C K7B321835C 1Mx36 & 2Mx18 Synchronous SRAM 36Mb Sync. Burst SRAM Specification 100LQFP with Pb / Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.
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