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K4S51323LF-MEL - 4M x 32Bit x 4 Banks Mobile SDRAM

Download the K4S51323LF-MEL datasheet PDF. This datasheet also covers the K4S51323LF-MC variant, as both devices belong to the same 4m x 32bit x 4 banks mobile sdram family and are provided as variant models within a single manufacturer datasheet.

General Description

The K4S51323LF is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Key Features

  • VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V.
  • LVCMOS compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
  • EMRS cycle with address key programs.
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • Special Function Support.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K4S51323LF-MC_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S51323LF-MEC 4M x 32Bit x 4 Banks Mobile SDRAM
K4S51323LF-MEF 4M x 32Bit x 4 Banks Mobile SDRAM
K4S51323LF-MC 4M x 32Bit x 4 Banks Mobile SDRAM
K4S51323LF-MF 4M x 32Bit x 4 Banks Mobile SDRAM
K4S51323LF-ML 4M x 32Bit x 4 Banks Mobile SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K4S51323LF - M(E)C/L/F 4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25°C ~ 70°C). • 2Chips DDP 90Balls FBGA ( -MXXX -Pb, -EXXX -Pb Free).