K4S51323LF-MEC Datasheet PDF (4M x 32Bit x 4 Banks Mobile SDRAM) | Download Samsung semiconductor K4S51323LF-MEC

K4S51323LF-MEC - 4M x 32Bit x 4 Banks Mobile SDRAM

This page provides the datasheet information for the K4S51323LF-MEC, a member of the K4S51323LF-MC 4M x 32Bit x 4 Banks Mobile SDRAM family.

Description

The K4S51323LF is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Features

VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation.
Special Function Support.

Datasheet Details

Part number	K4S51323LF-MEC
Manufacturer	Samsung semiconductor
File Size	172.62 KB
Description	4M x 32Bit x 4 Banks Mobile SDRAM
Datasheet	K4S51323LF-MEC Datasheet
Additional preview pages of the K4S51323LF-MEC datasheet.

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Full PDF Text Transcription

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K4S51323LF - M(E)C/L/F 4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25°C ~ 70°C). • 2Chips DDP 90Balls FBGA ( -MXXX -Pb, -EXXX -Pb Free).

Published: Apr 12, 2010 |