K4S51323LF-MEC Overview
Description
The K4S51323LF is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle.
Key Features
- VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V
- LVCMOS compatible with multiplexed address
- Four banks operation
- EMRS cycle with address key programs
- All inputs are sampled at the positive going edge of the system clock
- Burst read single-bit write operation
- Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh)
- DQM for masking
- Auto refresh
- 64ms refresh period (8K cycle)
