K4S51323LF-MEC Datasheet | Samsung Semiconductor

FEATURES - VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V. - LVCMOS patible with multiplexed address. - Four banks operation. - MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). - EMRS cycle with address key programs. - All inputs are sampled at the positive going edge of the system clock. - Burst read single-bit write operation. - Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature pensated Self Refresh) - DQM for masking. - Auto refresh. - 64ms refresh period (8K cycle). - mercial Temperature Operation (-25°C ~ 70°C). - 2Chips DDP 90Balls FBGA ( -MXXX -Pb, -EXXX -Pb Free). Mobile SDRAM .. GENERAL DESCRIPTION The K4S51323LF is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. K4S51323LF-M(E)C/L/F75 K4S51323LF-M(E)C/L/F1H K4S51323LF-M(E)C/L/F1L Max Freq. 133MHz(CL=3), 111MHz(CL=2) 111MHz(CL=2) 111MHz(CL=3)- 1, 83MHz(CL2) LVCMOS 90 FBGA Pb (Pb Free) Interface Package - M(E)C/L/F : Normal / Low / Low Power, mercial Temperature(-25°C ~ 70°C) NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic DRAM" for use as ponents in general and scientific puters such as, by way of example, mainframes, servers, work stations or desk top puters for the first three years of five year term of this license. Nothing herein limits the...