Architecture
•
•
•
•
•
•
Cache Memory & internal SRAM
•
•
•
•
•
•
Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC architecture and powerful instruction set with ARM7TDMI CPU core.
4-way set associative ID(Unified)-cache with 8Kbyte. The 0/4/8 Kbytes inter.