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K7A403600M - 128K x 36 Synchronous SRAM

General Description

The K7A403600M is a 4,718,592-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System.

Key Features

  • Synchronous Operation.
  • 2 Stage Pipelined operation with 4 Burst.
  • On-Chip Address Counter.
  • Self-Timed Write Cycle.
  • On-Chip Address and Control Registers.
  • VDD= 3.3V+0.3V/-0.165V Power Supply.
  • VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O.
  • 5V Tolerant Inputs Except I/O Pins.
  • Byte Writable Function.
  • Global Write Enable Controls a full bus-width write.
  • P.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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K7A403600M Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM 128Kx36 Synchronous SRAM Revision History Rev. No. 0.0 0.1 0.2 0.3 History Initial draft Change 7.5 bin to 7.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85 Draft Date May . 15. 1997 January . 13 . 1998 February. 02. 1998 Remark Preliminary Preliminary Preliminary Preliminary Change DC characteristics VDD condition from VDD=3.3V+10%/-5% Change February. 12. 1998 Input/output leackage currant for ±1µA to ±2µA Modify Read timing & Power down cycle timing. Change ISB2 value from 30mA to 20mA. Remove DC characteristics ISB1 - L ver.& ISB2 - L ver . Remove Low power version. Add 119BGA(7x17 Ball Grid Array Package) Change Undershoot spec from -3.0V(pulse width≤20ns) to -2.0V(pulse width≤tCYC/2) Add Overshoot spec 4.