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STU/D412S
S a mHop Microelectronics C orp.
Ver 1.0
N-Channel Logic Level Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY
V DSS
40V
FEATURES Super high dense cell design for low R DS(ON). Rugged and reliable. TO-252 and TO-251 Package.
ID
22A
R DS(ON) (m Ω) Max
26 @ VGS=10V 40 @ VGS=4.5V
ESD Protected.
D
D G S
G D
G
S
STU SERIES TO-252AA(D-PAK)
STD SERIES TO-251(l-PAK)
S
ABSOLUTE Symbol VDS VGS ID IDM EAS PD TJ, TSTG
MAXIMUM RATINGS ( T C=25 °C unless otherwise noted ) Parameter Drain-Source Voltage Gate-Source Voltage TA=25 °C a Drain Current-Continuous TA=70 °C -Pulsed b Avalanche Energy
c
Limit 40 ±20 22 17.