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SPP2319W Datasheet Preview

SPP2319W Datasheet

P-Channel MOSFET

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SPP2319W
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP2319W is the P-Channel logic enhancement
mode power field effect transistors are produced using
high cell density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits where high-side switching , and low in-line
power loss are needed in a very small outline surface
mount package.
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
FEATURES
-40V/-3.0A,RDS(ON)=100mΩ@VGS=- 10V
-40V/-2.8A,RDS(ON)=130mΩ@VGS=-4.5V
Super high density cell design for extremely low
RDS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-23 package design
PIN CONFIGURATION ( SOT-23 )
PART MARKING
2009/07/15 Ver.1
Page 1




SYNC POWER

SPP2319W Datasheet Preview

SPP2319W Datasheet

P-Channel MOSFET

No Preview Available !

SPP2319W
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
Symbol
G
S
D
Description
Gate
Source
Drain
ORDERING INFORMATION
Part Number
Package
SPP2319WS23RGB
SOT-23
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
SPP2319WS23RGB : Tape Reel ; Pb Free ; Halogen Free
Part Marking
S19WYW
ABSOULTE MAXIMUM RATINGS
(TA=25Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate Source Voltage
Continuous Drain Current(TJ=150)
Pulsed Drain Current
TA=25
TA=70
Continuous Source Current(Diode Conduction)
Power Dissipation
TA=25
TA=70
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
Symbol
VDSS
VGSS
ID
IDM
IS
PD
TJ
TSTG
RθJA
2009/07/15 Ver.1
Typical
-40
±20
-3.5
-2.8
-20
-1.4
1.25
0..81
-55/150
-55/150
105
Unit
V
V
A
A
A
W
/W
Page 2


Part Number SPP2319W
Description P-Channel MOSFET
Maker SYNC POWER
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SPP2319W Datasheet PDF






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