STM8AH51AA
Overview
- Max fCPU: 24 MHz
- Advanced STM8A core with Harvard architecture and 3-stage pipeline
- Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark LQFP48 7x7 LQFP80 14x14 LQFP64 10x10 LQFP32 7x7 Memories
- Communication interfaces *
- Program memory: 48 to 128 Kbytes Flash; data retention 20 years at 55 °C after 1 kcycle
- Data memory: 1.5 to 2 Kbytes true data EEPROM; endurance 300 kcycles
- RAM: 3 to 6 Kbytes Clock management
- Low power crystal resonator oscillator with external clock input
- Internal, user-trimmable 16 MHz RC and low power 128 kHz RC oscillators
- Clock security system with clock monitor High speed 1 Mbit/s active CAN 2.0B interface USART with clock output for synchronous operation - LIN master mode
