STM8AH51AA Overview
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STM8AH51AA Key Features
- Max fCPU: 24 MHz
- Advanced STM8A core with Harvard architecture and 3-stage pipeline
- Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark
- munication interfaces
- Data memory: 1.5 to 2 Kbytes true data EEPROM; endurance 300 kcycles
- RAM: 3 to 6 Kbytes
- Low power crystal resonator oscillator with external clock input
- Internal, user-trimmable 16 MHz RC and low power 128 kHz RC oscillators
- Clock security system with clock monitor
- LIN master mode