STM32WL5MOC Datasheet | STMicroelectronics

STM32WL5MOC Datasheet Multiprotocol LPWAN dual-core module 32-bit Arm® Cortex®-M4/M0+ LoRa®, (G)FSK, (G)MSK, BPSK LGA92 (10x10 mm) Non-contractual images Product status link STM32WL5MOC Features Includes ST state-of-the-art patented technology. Integration of STM32WL55JC: - Dual-core Arm® Cortex®-M0 and Arm® Cortex®-M4 CPU - ART Accelerator with a speed of up to 48 MHz - 256-Kbyte flash memory - 64- Kbyte SRAM with sub-GHz radio transceiver - Embedded 32 MHz radio TCXO and 32 kHz RTC crystals - All RF ponents for transmission and reception matching network, including default antenna filter - STSAFE-A110 footprint - Metal shield coating Supporting: - Frequencies from 864 MHz to 928 MHz - patible with standardized or proprietary protocols such as LoRaWAN®, Sigfox™, or W- MBus (fully open wireless system-on-chip mioty). - pliant with radio frequency regulations such as ETSI EN 300 220, FCC CFR 47 Part 15, and Japanese ARIB STD- T-108: - FCC ID: YCP-32WL5MOCH01 - IC: 8976A-32WL5MOCH01 - If other power or modulation settings than the type documented in the FCC and ISED-Canada filings are used, a class 2 permissive change must be filed with FCC and ISED. - Rx sensitivity: - 123 dBm for 2-FSK (at 1.2 Kbit/s), - 148 dBm for LoRa® (at 10.4 kHz, spreading factor 12) - Transmitter high output power, programmable up to +22 dBm...