* Includes ST state-of-the-art patented technology
* Core: Arm® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator and L1-cache: 16 Kbytes I/D cache, allowing 0-wa.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Arm® Cortex®-M7 with FPU . . . . . . . .

+FPU

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