STDVE001A Datasheet | STMicroelectronics

Features - patible with the high-definition multimedia interface (HDMI) v1.3 digital interface - Conforms to the transition minimized differential signaling (TMDS) voltage standard on input and output channels - 340 MHz maximum clock speed operation supports all video formats with deep color at maximum refresh rates - 3.4 Gbps data rate per channel - Fully automatic adaptive equalizer for cables lengths up to 25 m - Single supply VCC: 3.135 to 3.465 V - ESD: ±8 KV contact for all I/Os - Integrated open-drain I2C buffer for display data channel (DDC) - 5.3 V tolerant DDC and HPD I/Os - Lock-up free operation of I2C bus - 0 to 400 k Hz clock frequency for I2C bus - Low capacitance of all the channels - Equalizer regenerates the ining attenuated TMDS signal - Buffer drives the TMDS outputs over long PCB track lengths - Low output skew and jitter - Tight input thresholds reduce bit error rates - On-chip selectable 50 Ω input termination - Low ground bounce - Data and control inputs provide undershoot clamp diode - Evaluation kit is available Table 1. Device summary Order code Operating temperature STDVE001ABTR STDVE001AQTR -40°C to 85°C -40°C to 85°C TQFP48 QFN48 Description The STDVE001A integrates a 4-channel 3.4 Gbps TMDS equalizer. High-speed data paths and flowthrough pinout minimize the internal device jitter and simplify the board layout. The equalizer overes the intersymbol interference (ISI) jitter effects from lossy cables. The buffer/driver on the output can drive the TMDS output signals over long distances. In addition to this, STDVE001A integrates the 50 Ω termination resistor on all the input channels to improve performance and reduce board space. The device can be placed in a low-power mode by disabling the output current drivers. The STDVE001A is ideal for advanced TV and STB applications supporting HDMI/DVI standard. The differential signal from the HDMI/DVI ports can be routed through the STDVE001A to guarantee good signal quality at the HDMI...