ST70136 Datasheet | STMicroelectronics

CPE ADSL ANALOG FRONT END s WIDE TRANSMIT AND RECEIVE DYNAMIC s s s s s s s s s s s s RANGE TO REDUCE EXTERNAL FILTERING REQUIREMENTS RECEIVE PROGRAMMABLE GAIN: 0 TO 31d B GAIN IN 1d B STEPS RECEIVE PROGRAMMABLE ATTENUATOR 0,-4d B, -8d B, -12d B 12-BIT A/D CONVERTER IN RECEIVE PATH TRANSMIT PROGRAMMABLE GAIN: 0 TO -15d B IN 1d B STEPS 14-BIT D/A CONVERTER IN TRANSMIT PATH LOW POWER MODE: 10m W IN LISTENING MODE, 250µW IN POWER DOWN TONE DETECTOR: ACTIVITY DETECTION FOR WAKE-UP FUNCTION 64-PIN TQFP PACKAGE 64-PIN LFBGA PACKAGE 0.50µm, 5V BICMOS TECHNOLOGY 3.3V DIGITAL INTERFACE 5V ANALOG INTERFACE The AFE receive path contains a programmable gain amplifier (Rx PGA), a low pass anti-aliasing filter, and a 12-bit A/D converter. The Rx PGA is digitally programmable from 0 to 31d B in 1d B steps. The AFE transmit path consists of a 14-bit D/A converter, followed by a programmable gain amplifier (Tx PGA). The transmit gain is programmable from 0 to -15d B in 1d B steps. TQFP64 Full Plastic (10 x 10 x 1.40 mm) ORDER CODE: ST70136G INTRODUCTION The ST70136 ADSL Analog Front End (AFE) chip implements the analog transceiver functions required in a Customer Premise ADSL modem. It connects the digital modem chip with the loop driver and hybrid balance circuits. The AFE has been designed with high dynamic range in order to greatly reduce the external filtering requirements at the front end. The AFE chip and its panion digital chip along with a loop driver, implement the plete G.992.2 and G.992.1 DMT modem solution. Figure 1 : Overall Application Block Diagram Software for Control x DSL LFBGA64 (8 x 8 x 1.7 mm) ORDER CODE: ST70136B PCI or USB PCI or USB LINE DMT x DSL AFE LOOP DRIVER HYBRID ST70137 TS612/TS652 September 2001 1/24 ST70136 Pinout VDDOSC VCOCAP VCXOUT VSSOSC VSSESD VDDA6 VDDA5 50 48 VSDA VDDA4 PGAP TXIN TXP TXN TXIP PGAN VSSA4 VSSA3 V290DA V125AD V250AD 35 34 33 V375AD VSBIAS V3P75V 47 46 45 44 43 42 41 49 VSSA5 40 39 38 37 36 32...