M74HC590 Datasheet | STMicroelectronics

DESCRIPTION The M74HC590 is an high speed CMOS 8-BIT BINARY COUNTER REGISTER (3 STATE) fabricated with silicon gate C2MOS technology. This device contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features a direct clear input CCLR and a count enable input CCKEN. For cascading, a ripple carry output RCO is provided. Expansion is easily acplished by tying RCO of the first stage to CCKEN of the second stage, etc. Both the counter and register clocks are positive edge triggered. If the user wishes to connect both clocks together, the counter state will always be one count ahead of the register. Internal circuitry prevents clocking from the clock enable. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/15 .Data Sheet.in INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 3, 4, 5, 6, 7, 15 11 12 13 9 14 10 8 16 SYMBOL QA to QH CCK CCKEN RCK RCO G CCLR GND VCC NAME AND FUNCTION Outputs Counter Clock Input Counter Clock Enable Input Register Clock Input Ripple Carry Output Output Enable Input Counter Clear Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUT G H L X X X X X X X X X X RCK X X CCLR X X X X L H H H CCKEN X X X X X L L H X CCK X X X X X Q OUTPUTS DISABLE Q OUTPUTS ENABLE COUNTER DATA IS STORED INTO REGISTER REGISTER STAGE IS NOT CHANGED COUNTER CLEAR ADVANCE ONE COUNT NO COUNT NO COUNT X: Don’t Care RCO = QA’- QB’- QC’- QD’- QE’- QF’- QG’- QH’ (QA’ to QH’ : INTERNAL OUTPUTS OF THE COUNTER) LOGIC DIAGRAM 2/15 .Data Sheet.in LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 3/15 .Data Sheet.in TIMING CHART 4/15 .Data Sheet.in ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Supply Voltage DC...