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M74HC40102 Datasheet

8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

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M54/74HC40102
M54/74HC40103
8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
. HIGH SPEED
fMAX = 40 MHz (TYP.) at VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) at TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V to 6 V
. PIN AND FUNCTION COMPATIBLE WITH
40102B/40103B
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXXXF1R M74HCXXXXXM1R
M74HCXXXXXB1R M74HCXXXXX C1R
DESCRIPTION
The M54/74HC40102/40103 are high speed CMOS
8-STAGE PRESETTABLE SYNCHRONOUS
DOWN COUNTERS fabricated with silicon gate
C2MOS technology. They achieve the high speed
operation similar to equivalent LSTTL while main-
taining the CMOS low power dissipation.
The HC40102, and HC40103 consist of an 8-stage
synchronous down counter with a single output
which is active when the internal count is zero. The
HC40102 is configured as two cascaded 4-bit BCD
counters, and the HC40103 contains a single 8-bit
binary counter. Each type has control inputs for en-
abling or disabling the clock, for clearing the counter
to its maximum count, and for presetting the counter
either synchronously or asynchronously. All control
inputs and the CARRY-OUT/ZERO-DETECT out-
put are active-low logic. In normal operation, the
counter is decremented by one count on each posi-
tive transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/CE)
input is high. The CARRY-OUT/ZERO-DETECT
(CO/ZD) output goes low when the count reaches
zero if the CI/CE input is low, and remains low for
one full clock period. When the SYNCHRONOUS
PRESET-ENABLE (SPE) input is low, data at the J
input is clocked into the counter on the next positive
clock transition regardless of the state of the CI/CE
input.
March 1993
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
1/14


STMicroelectronics Electronic Components Datasheet

M74HC40102 Datasheet

8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

No Preview Available !

M54/M74HC40102/40103
DESCRIPTION (Continued)
When the ASYNCHRONOUS PRESET-ENABLE
(APE) input is low, data at the J inputs is asynchron-
ously forced into the counter regardless of the state
of the SPE, CI/CE, or CLOCK inputs. J Inputs J0-J7
represent two 4-bit BCD words for the HC40102 and
a single 8-bit binary word for the HC40103. When
the CLEAR (CLR input is low, the counter is asyn-
chronously cleared to its maximum count (9910 for
the HC40102 and 25510 for the HC40103 regard-
less of the state of any other input. The precedence
relationship between control input is indicated in the
truth table. If all control inputs are high at the time of
zero count, the counters will jump to the maximum
count, giving a counting sequence of 100 pr 256
clock pulses long. The HC40102 and HC40103 may
be cascaded using the CI/CE input and the CO/ZD
output, in either a synchronous or ripple mode. All
inputs are equipped with protection circuits against
static discharge and transient excess voltage.
TRUTH TABLE
CONTROL INPUTS
CLEAR APE SPE CI/CE
MODE
FUNCTIONAL DESCRIPTION
H H H H COUNT INHIBIT
EVEN IF CLOCK IS GIVEN, NO COUNT IS
MADE
H H H L REGULAR COUNT
DOWN COUNT AT RISING EDGE OF CLOCK
H H L X SYNCHRONOUS PRESET DATA OF PI TERMINAL IS PRESET AT
RISING EDGE OF CLOCK
H L X X ASYNCRONOUS PRESET DATA PF PI TERMINAL IS
ASYNCHRONOUSLY PRESET TO CLOCK
L X X X CLEAR
COUNTER IS SET TO MAXIMUM COUNT
X: DON’T CARE - MAXIMUM COUNT: ”99” FOR HC40102 AND ”255”: FOR HC40103
LOGIC DIAGRAM (HC40102)
2/14


Part Number M74HC40102
Description 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS
Maker ST Microelectronics
Total Page 14 Pages
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