M74HC109 Datasheet | STMicroelectronics

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR s HIGH SPEED : f MAX = 67MHz (TYP.) at VCC = 6V s LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = VNIL = 28 % VCC (MIN.) s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4m A (MIN) s BALANCED PROPAGATION DELAYS: t PLH ≅ t PHL s WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION PATIBLE WITH 74 SERIES 109 DESCRIPTION The M74HC109 is an high speed CMOS DUAL J-K FLIP FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. In accordance with the logic level on the J and K input this device changes state on positive going transition of the clock pulse. CLEAR and PRESET TSSOP ORDER CODES PACKAGE TUBE DIP SOP TSSOP M74HC109B1R M74HC109M1R T&R M74HC109RM13TR M74HC109TTR are independent of the clock and are acplished by a logic low on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1,15 2, 14, 3, 13 4, 12 5, 11 6, 10 7, 9 8 16 1CLR, 2CLR Asynchronous Reset Direct Input 1J, 2J, 1K, Synchronous Inputs; 2K Flip-Flops 1 and 2 1CK, 2CK Clock Input 1PR, 2PR Asynchronous Set Direct Input (Active Low) 1Q, 2Q True Flip-Flop Outputs 1Q, 2Q plement Flip-Flop...