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STMicroelectronics Electronic Components Datasheet

74VHC238 Datasheet

3 TO 8 LINE DECODER

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74VHC238
3 TO 8 LINE DECODER
s HIGH SPEED: tPD = 5.5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
)s POWER DOWN PROTECTION ON INPUTS
t(ss SYMMETRICAL OUTPUT IMPEDANCE:
c|IOH| = IOL = 8 mA (MIN)
us BALANCED PROPAGATION DELAYS:
dtPLH tPHL
ros OPERATING VOLTAGE RANGE:
PVCC(OPR) = 2V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
te74 SERIES 238
les IMPROVED LATCH-UP IMMUNITY
bsoDESCRIPTION
The 74VHC238 is an advanced high-speed
- OCMOS 3 TO 8 LINE DECODER fabricated with
)sub-micron silicon gate and double-layer metal
t(swiring C2MOS technology.
If the device is enabled, 3 binary select inputs (A,
cB, and C) determine which one of the outputs will
ugo high. If enable input G1 is held low or either
rodG2A or G2B is held high, decoding function is
inhibited and all the 8 outputs go to low.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74VHC238MTR
74VHC238TTR
Tree enable inputs are provided to ease cascade
connection and application of address decoders
for memory systems.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Obsolete PFigure 1: Pin Connection And IEC Logic Symbols
November 2004
Rev. 4
1/12


STMicroelectronics Electronic Components Datasheet

74VHC238 Datasheet

3 TO 8 LINE DECODER

No Preview Available !

74VHC238
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL NAME AND FUNCTION
1, 2, 3
4, 5
6
15, 14, 13,
12, 11, 10, 9,
7
8
16
A, B, C
G2A, G2B
G1
Y0 to Y7
Address Inputs
Enable Inputs
Enable Input
Outputs
GND
VCC
Ground (0V)
Positive Supply Voltage
t(s)Table 3: Truth Table
cINPUTS
duENABLE
SELECT
roG2B G2A G1
C
B
A
PX X L X X X
teX H X X X X
leH X X X X X
oL L H L L L
bsL L H L L H
OL L H L H L
-L L H L H H
)L L H H L L
t(sL L H H L H
cL L H H H L
uL L H H H H
rodX : Don’t care
Obsolete PFigure 3: Logic Diagram
OUTPUTS
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
LLLLLLLL
LLLLLLLL
LLLLLLLL
HL L L L L L L
LHL L L L L L
L LHL L L L L
L L LHL L L L
L L L LHL L L
L L L L LHL L
L L L L L LHL
L L L L L L LH
This logic diagram has not be used to estimate propagation delays
2/12


Part Number 74VHC238
Description 3 TO 8 LINE DECODER
Maker STMicroelectronics
Total Page 12 Pages
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