74AC373 Datasheet | STMicroelectronics

DESCRIPTION state (high or low logic level) and while high level The AC373 is an advanced high-speed CMOS the outputs will be in a high impedance state. .. OCTAL D-TYPE LATCH with 3 STATE OUTPUT This device is designed to interface directly High NON INVERTING fabricated with sub-micron Speed CMOS systems with TTL and NMOS 2 silicon gate and double-layer metal wiring C MOS ponents. technology. It is ideal for low power applications All inputs and outputs are equipped with mantaining high speed operation similar to protection circuits against static discharge, giving equivalent Bipolar Schottky TTL. them 2KV ESD immunity and transient excess These 8 bit D-Type latch are controlled by a latch voltage. enable input (LE) and an output enable input s HIGH SPEED: t PD = 5 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 o C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 m A (MIN) BALANCED PROPAGATION DELAYS: t PLH ≅ t PHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION PATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74AC373B 74AC373M PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND F UNCTIO N 3 State Output Enable Input (Active LOW) Data Inputs D0 to D7 3 State Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUT S OE H L L L LE X L H H D X X L H OUT PUT S Q Z NO CHANGE L H X: DON’T CARE Z: HIGH IMPEDANCE - : Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE INPUT IS TAKEN LOW LOGIC LEVEL. LOGIC DIAGRAMS 2/10 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output...