Peripheral Interface Adapter/Timer (PIAT)
Blank = D°C to + 70°C
E = -4 0 °C to + 85°C
1 = 1 MHz
2 = 2 MHz
3 = 3 MHz
4 = 4 MHz
C = 40-Pin Ceramic DIP
P = 43-Pin Plastic DIP
j = 44-Pin Plastic Leaded
Chip Carrier (PLCC)
An R65C24 PIAT may be installed in a circuit in place of
an R65C21 PIA subject to chip select considerations. Since
the R65C21 has a CS1 input and the R54C24 does not
have a CS1 input, the PIAT will be selected in the same
addresses as the PIA and maybe more depending upon
external address decoding circuitry.
RESET SIGNAL (RES)
The Reset (RES) input initializes the R65C24 PIAT. A low signal
on the (RES) input causes all internal registers to be cleared.
CLOCK SIGNAL (02)
The Phase 2 Clock Signal (02) is the system clock that triggers
all data transfers between the CPU and the PIAT. 02 is generated
by the CPU and is therefore the synchronizing signal between
the CPU and the PIAT.
The PIAT interfaces to the R6500, R6500/* or the R65COO
microprocessor family with a reset line, a 02 clock line, a
read/write line, an interrupt request line, three register select lirves,
two chip select lines, and an 8-bit bidirectional data bus.
The PIAT interfaces to the peripheral devices with four
interrupt/control lines and two 8-bit bidirectional data ports. A
Counter/Timer input/output line (CNTR) also interfaces to a
Figure 1 (on the front page) shows the pin assignments for these
interface signals and Figure 2 shows the interface relationship of
these signal as they pertain to the CPU and the peripheral devices.
CHIP SELECT (CSO, CS2)
The PIAT is selected when CSO is high and CS2 is low. These
two chip select lines are normally connected to the processor
address lines either directly or through external decoder circuits.
When the PIAT is selected, data will be transferred between the
data lines and PIAT registers, and/or peripheral interface lines
as determined by the R/W, RSO, RS1 and RS2 lines and the
contents of Control Registers A and B.
READ/WRITE SIGNAL (R/W)
Read/Write (R/W) controls the direction of data transfers between
the PIAT and the data lines associated with the CPU and the
peripheral devices. A high on the R/W line permits the peripheral
devices to transfer data to the CPU from the PIAT. A low on the
R/W line allows data to be transferee) from the CPU to the
peripheral devices from the PIAT.
REGISTER SELECT (RSO, RS1, RS2)
Two of the Register Select lines (RSO, RS1), in conjunction with
the Control Registers (CRA, CRB), select various R65C24
registers to be accessed by the CPU. RSO and RS1 are normally
connected to the microprocessor (CPU) address output lines.
Through control o f these lines, the CPU can w rite directly into
the Control Registers (CRA, CRB), the Data Direction Registers
(DDRA, DDRB)and the Peripheral Output Registers (OFtA, ORB).
In addition, the processor may directly read the contents of the
Control Registers and the Data Direction Registers. Accessing
the Peripheral Output Register for ihe purpose of reading data
back into the processor operates differently on the ORA and the
ORB registers and, therefore, are shown separately in Table 1.
Figure 2. Interface Signals Relationship