All R650011 interface signals are available in the R6500l1E
microcomputer plus the additional address (12), data (8), and con-
trol (4) lines required to extend the address bus and the data bus
external to the device. The R6500/1E emulator unique interface
signals are shown in Figure 1 and are described in Table 1. While
the pin assignments are different in order to accommodate
64-pin DIP and QUIP packages, the interface characteristics of
signals common to the R650011 are identical.
The architecture of the R6500l1E is identical to the R6500/1 with
the following differences:
ROM addressing is routed externally in the R650011E. The address
range for internal ROM in the R6500/1 ($800-$FF9) is available
externally for connection to ROM or RAM devices(s).
An additional 1024 bytes ($400-$7FF) are decoded for external
memory access. Note that this address range can be used for
Microprocessor Emulator Device
debugging with the R650011E but cannot be used when the object
code is transferred to masked ROM in an R650011 (which is res-
tricted to $800-$FF9).
A memory map of the R6500l1E is shown in Figure 2.
INTERNAL 1/0 PORT PULL-UPS
The R6500/1E has the internal I/O and CNTR port pull-up resis-
tors only. The option to delete the pull-up resistors is not availa-
ble for the R6500/1 E.
EARLIER I/O PORT INITIALIZATION
Ports A, B, C, D and the CNTR line in the R6500/1 Eare initialized
to the logic high state two 02 clock cycles earlier than in the
ResOO/l.lt is still required, however, thatthe RES line be held low
for at least eight 02 clock cycles after VCC reaches operating range
The R6500l1E allows the user to monitor write operations to the
internal RAM and I/O by routing those operations externally as well
as internally. Read operations are not routed externally.
Figure 1. R6500/1E Emulator Interface Diagram