UPD48011336 dram equivalent, low latency dram.
* 1 cycle 600MHz DDR Muxed Address
* Optional data bus inversion to reduce SSO, SSN, maximum I/O current, and average I/O power
* Training sequence for per-bi.
implementing error correction), excluding refresh overhead and data bus turn-around
With a bus speed of 600 MHz, a burst.
The μPD48011318 is a 67,108,864-word by 18-bit and the μPD48011336 is a 33,554,432-word by 36-bit synchronous
double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor eDRAM memory cell. The Low Latency DRAM-III c.
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