R5F571MGCDLC Datasheet | Renesas

Features RX71M Group Renesas MCUs R01DS0249EJ0100 Rev.1.00 240-MHz 32-bit RX MCU, on-chip FPU, 480 DMIPS, up to 4-MB flash memory, Jan 15, 2015 512-KB SRAM, various munications interfaces including IEEE 1588-pliant Ethernet MAC, high-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface Features - 32-bit RXv2 CPU core - Max. operating frequency: 240 MHz Capable of 480 DMIPS in operation at 240 MHz - Single precision 32-bit IEEE-754 floating point - Two types of multiply-and-accumulation unit (between memories and between registers) - 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) - Divider (fastest instruction execution takes two CPU clock cycles) - Fast interrupt - CISC Harvard architecture with 5-stage pipeline - Variable-length instructions: Ultra-pact code - Supports the memory protection unit (MPU) - JTAG and FINE (one-line) debugging interfaces - Low-power design and architecture - Operation from a single 2.7- to 3.6-V supply - Low power consumption: A product that supports all peripheral functions draws only 0.2m A/MHz (Typ.). - RTC is capable of operation from a dedicated power supply. - Four low-power modes - On-chip code flash memory - Supports versions with up to 4 Mbytes of ROM - No wait states at up to 120 MHz or when the AFU is hit, one wait state at above 120 MHz and when the AFU is missed - User code is programmable by on-board or off-board programming. - Programming/erasing as background operations (BGOs) - On-chip data flash...