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R5F52206BGFM - 32-MHz 32-bit RX MCUs

Download the R5F52206BGFM datasheet PDF. This datasheet also covers the R5F52206BDFP variant, as both devices belong to the same 32-mhz 32-bit rx mcus family and are provided as variant models within a single manufacturer datasheet.

Features

  • 32-bit RX CPU core.
  • Max. operating frequency: 32 MHz.
  • Capable of 49 DMIPS in operation at 32 MHz.
  • Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
  • Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
  • Fast interrupt.
  • CISC Harvard architecture with 5-stage pipeline.
  • Variable-length instructions, ultra-compact code.
  • On-chip debugging circuit.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (R5F52206BDFP_Renesas.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Datasheet RX220 Group Renesas MCUs 32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory, 12-bit A/D, ELC, MPC, IrDA, RTC, up to 7 comms channels; incorporating functions for IEC60730 compliance R01DS0130EJ0110 Rev.1.10 Dec 20, 2013 Features ■ 32-bit RX CPU core  Max. operating frequency: 32 MHz  Capable of 49 DMIPS in operation at 32 MHz  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions, ultra-compact code  On-chip debugging circuit ■ Low-power design and architecture  Operation from a single 1.62-V to 5.
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