Datasheet4U Logo Datasheet4U.com

R5F52206BGFK - 32-MHz 32-bit RX MCUs

This page provides the datasheet information for the R5F52206BGFK, a member of the R5F52206BDFP 32-MHz 32-bit RX MCUs family.

Features

  • 32-bit RX CPU core.
  • Max. operating frequency: 32 MHz.
  • Capable of 49 DMIPS in operation at 32 MHz.
  • Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
  • Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
  • Fast interrupt.
  • CISC Harvard architecture with 5-stage pipeline.
  • Variable-length instructions, ultra-compact code.
  • On-chip debugging circuit.

📥 Download Datasheet

Datasheet preview – R5F52206BGFK

📁 Similar Datasheet

  • R5F10xxxxxx - Combines Multi-channel 12-Bit A/D Converter (Renesas Technology)
  • R5F211A1DD - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A1DSP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A1SP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A2DD - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A2DSP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A2NP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A2SP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A3DD - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
  • R5F211A3DSP - 16-BIT SINGLE-CHIP MICROCOMPUTER (Renesas Technology)
Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
Datasheet RX220 Group Renesas MCUs 32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory, 12-bit A/D, ELC, MPC, IrDA, RTC, up to 7 comms channels; incorporating functions for IEC60730 compliance R01DS0130EJ0110 Rev.1.10 Dec 20, 2013 Features ■ 32-bit RX CPU core  Max. operating frequency: 32 MHz  Capable of 49 DMIPS in operation at 32 MHz  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions, ultra-compact code  On-chip debugging circuit ■ Low-power design and architecture  Operation from a single 1.62-V to 5.
Published: |