R5F52106ADLJ, R5F52108ADFP Datasheet - Renesas

R5F52106ADLJ 50-MHz 32-bit RX MCUs

* * * * * Maximum operating frequency: 50 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Ac.

R5F52106ADLJ Features

* 32-bit RX CPU core

* Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz

* Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations

* Multiplication and division unit handles 32- × 32-bit operations (multiplication instructi

R5F52108ADFP_Renesas.pdf