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R5F51303ADFK - 32-bit RX MCUs

Download the R5F51303ADFK datasheet PDF. This datasheet also covers the R5F51305ADFN variant, as both devices belong to the same 32-bit rx mcus family and are provided as variant models within a single manufacturer datasheet.

Description

CPU CPU Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One 64-bit

Features

  • 32-bit RX CPU core.
  • Max. operating frequency: 32 MHz Capable of 50 DMIPS in operation at 32 MHz.
  • Accumulator handles 64-bit results (for a single instruction) from 32-bit × 32-bit operations.
  • Multiplication and division unit handles 32-bit × 32-bit operations (multiplication instructions take one CPU clock cycle).
  • Fast interrupt.
  • CISC Harvard architecture with 5-stage pipeline.
  • Variable-length instructions, ultra-compact code.
  • On-chip debugging circuit.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (R5F51305ADFN-Renesas.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Datasheet RX130 Group Renesas MCUs 32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 128-KB flash memory, R01DS0273EJ0100 Rev.1.00 Oct 30, 2015 up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply Features ■ 32-bit RX CPU core  Max.
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