R1QEA3618CBG Renesas Datasheet

R1QEA3618CBG Key Features

• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with Ps restart
• mon data input/output bus
• Pipelined double data rate operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling